Abstract

A system with source and destination telecommunications transceivers for communicating therebetween over an Integrated Digital Services Network, each having a general purpose computer coupled to an interface circuit for conditioning outgoing and incoming data to and from the communications network. The interface circuit is constructed with a dual port RAM, a subscriber access controller and an ISDN controller. A typical data flow proceeds with the source controller CPU sending bytes of data from a sending buffer in its memory to a first transmit buffer in the dual port RAM. This process continues until the last address in the buffer is filled, whereupon the dual port RAM outputs an interrupt signal to the ISDN controller which responds by sending the data bytes in the buffer to the subscriber access controller for transmission to the ISDN, and sends a control signal instructing the computer to load a second transmit buffer. When the first buffer is emptied the ISDN controller instructs the computer to load the second, etc until all the data is transmitted. When data is being received from the ISDN by the subscriber access controller, it send an interrupt signal to the ISDN controller to hold outgoing data and transfer the incoming data to the computer. The ISDN controller loads the incoming data into one of two receive buffers, and when it is full, sends a signal to the computer to unload the data and proceeds to load the second receive buffer, after which the computer is notified to unload the second buffer. This process is repeated until the incoming data is processed. This process retains byte alignment throughout the interface circuit. In the event that the communications network should require data to be supplied in HDLC frame format, this is provided for by programming in the computer, as is the detection of incoming HDLC framed data and the required extraction of data bytes therefrom.