Substrate for dielectric isolated integrated circuit with V-etched depth grooves for lapping guide
Vapor epitaxial method for depositing gallium arsenide phosphide on germanium and silicon substrate wafers
Semiconductor device and method of manufacturing the same
Laser process for forming identically positioned alignment marks on the opposite sides of a semiconductor wafer
Method of producing a thin silicon-on-insulator layer
Using a rapid thermal process for manufacturing a wafer bonded soi semiconductor
Semiconductor heterostructures having Gex Si1-x layers on Si utilizing molecular beam epitaxy
ApplicationNo. 223098 filed on 04/04/1994
US Classes:148/33.2, With recess, void, dislocation, grain boundaries or channel openings257/E21.122, Bonding of semiconductor wafer to insulating substrate or to semic onducting substrate using an intermediate insulating layer (EPO)257/E21.567, Using bonding technique (EPO)438/479, On insulating substrate or layer438/977THINNING OR REMOVAL OF SUBSTRATE
ExaminersPrimary: Hearn, Brian E.
Assistant: Dang, Trung
Attorney, Agent or Firm
International ClassH01L 029/30
AbstractA method for fabricating silicon on insulator structures having a dislocation free silicon layer. The method utilizes low temperature UHVCVD to deposit a very heavily doped etch stop layer having a very steep doping profile onto a substrate and a lightly doped active layer onto the etch stop layer. An insulator is formed on the active layer and a carrier wafer is formed on the insulator layer. The original substrate is removed in a first etch and the etch stop layer is removed in a second etch resulting in a thin, uniform active layer. In one embodiment, a small percentage of germanium is added to the etch stop layer to produce a defect free epitaxial active layer.