Fabrication of defect free silicon on an insulating substrate

Patent 5540785 Issued on July 30, 1996. Estimated Expiration Date:

April 4, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

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Patent References

3293087

3455748

3829889

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Inventors

Application

No. 223098 filed on 04/04/1994

US Classes:

148/33.2, With recess, void, dislocation, grain boundaries or channel openings257/E21.122, Bonding of semiconductor wafer to insulating substrate or to semic onducting substrate using an intermediate insulating layer (EPO)257/E21.567, Using bonding technique (EPO)438/479, On insulating substrate or layer438/977THINNING OR REMOVAL OF SUBSTRATE

Examiners

Primary: Hearn, Brian E.
Assistant: Dang, Trung

Attorney, Agent or Firm

Scully, Scott, Murphy & Presser

International Class

H01L 029/30

Abstract

A method for fabricating silicon on insulator structures having a dislocation free silicon layer. The method utilizes low temperature UHVCVD to deposit a very heavily doped etch stop layer having a very steep doping profile onto a substrate and a lightly doped active layer onto the etch stop layer. An insulator is formed on the active layer and a carrier wafer is formed on the insulator layer. The original substrate is removed in a first etch and the etch stop layer is removed in a second etch resulting in a thin, uniform active layer. In one embodiment, a small percentage of germanium is added to the etch stop layer to produce a defect free epitaxial active layer.

Other References

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