Processor chip for parallel processing system
Patent 5535408 Issued on July 9, 1996. Estimated Expiration Date: 
May 2, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
May 2, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3312943 3582899 Array processors Method of and system for routing in a packet-switched communication network Massively parallel processor computer Microcomputer with automatic refresh of on-chip dynamic RAM transparent to CPU Extra stage cube Apparatus, methods, and systems for computer information transfer Patent #: 4644496 InventorAssigneeApplicationNo. 237981 filed on 05/02/1994US Classes:712/16, Array processor operation710/52, Input/Output data buffering711/106, Refresh scheduling712/13PartitioningExaminersPrimary: Eng, David Y.Attorney, Agent or FirmInternational ClassG06F 015/16AbstractA monolithic processing chip for a parallel processing system comprises a processor circuit and a memory circuit. The processor circuit processes data received from said associated memory circuit in accordance with processor control signals to generate processed data. The memory circuit includes a plurality of registers for storing data, each register including at least one data storage cell including at least one dynamic memory data bit store for storing a data bit. The memory circuit is responsive to memory control signals and register address signals to transmit stored data from the registers to the processor for processing and to store processed data received from the processor circuit in the register identified by the register address signals. | |
