Virtual processor module including a reconfigurable programmable matrix
Patent 5535406 Issued on July 9, 1996. Estimated Expiration Date: 
December 29, 2013. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
December 29, 2013. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesApparatus with reconfigurable counter includes memory for storing plurality of counter configuration files which respectively define plurality of predetermined counters Multibus sequential processor to perform in parallel a plurality of reconfigurable logic operations on a plurality of data sets Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor Patent #: 5361373 InventorApplicationNo. 175303 filed on 12/29/1993US Classes:712/10Array processorExaminersPrimary: Bowler, Alyssa H.Assistant: Harrity, John Attorney, Agent or FirmInternational ClassG06F 015/00AbstractA virtual processor has a reconfigurable, programmable logic matrix array for processing data in accord with a hardware encoded algorithm, a memory for storing a plurality of hardware configuration files for the programmable logic matrix array, each configuration file for programming an algorithm to be executed by the matrix array, an input/output bus for supplying data to the matrix array for processing and for obtaining processed data from the matrix array, a memory device for storing data, a VPM controller for controlling the overall operation of the virtual processor including providing operation sequence maps, providing parameters for specific operations, and providing status information, a data bus controller for controlling the data flow to the matrix array for processing, and a configuration controller for controlling the sequence of reconfiguration of the matrix array to process data by a specific sequence of algorithms.Other References
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