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US Patent 5535406 - Virtual processor module including a reconfigurable programmable matrix

US Patent Issued on July 9, 1996
Estimated Patent Expiration Date: Icon_subject December 29, 2013Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
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Abstract

A virtual processor has a reconfigurable, programmable logic matrix array for processing data in accord with a hardware encoded algorithm, a memory for storing a plurality of hardware configuration files for the programmable logic matrix array, each configuration file for programming an algorithm to be executed by the matrix array, an input/output bus for supplying data to the matrix array for processing and for obtaining processed data from the matrix array, a memory device for storing data, a VPM controller for controlling the overall operation of the virtual processor including providing operation sequence maps, providing parameters for specific operations, and providing status information, a data bus controller for controlling the data flow to the matrix array for processing, and a configuration controller for controlling the sequence of reconfiguration of the matrix array to process data by a specific sequence of algorithms.

Other References

  • Monaghan et al., "Reconfigurable Special Purpose Hardware For Scientific Computation And Simulation, " Computing And Control Engineering Journal, Sep. 1992, pp. 225-234
  • Sawyer et al., "Xilinx--The Third Generation," IEEE Colloquim On `User-Configurable Logic-Technology And Applications,` Mar. 1991, pp. 1/1-

Inventor

Application

No. 175303 filed on 12/29/1993

US Classes:

712/10Array processor

Examiners

Primary: Bowler, Alyssa H.
Assistant: Harrity, John

Attorney, Agent or Firm

US Patent References

5109503, Apparatus with reconfigurable counter includes memory for storing plurality of counter configuration files which respectively define plurality of predetermined counters
Issued on: 04/28/1992
Inventor: Cruickshank, et al.
5301344, Multibus sequential processor to perform in parallel a plurality of reconfigurable logic operations on a plurality of data sets
Issued on: 04/05/1994
Inventor: Kolchinsky
5361373Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
Issued on: 11/01/1994
Inventor: Gilson

International Class

G06F 015/00

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