Frequency controlled reference clock generator
Patent 5535067 Issued on July 9, 1996. Estimated Expiration Date: 
March 6, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
March 6, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesQuotient phase-shift processor for digital phase-locked-loops Zone servo sector format alignment scheme for servo and spindle motor control Phase lock loop for sector servo system Disk drive apparatus Track counting device using a PLL Patent #: 5309418 InventorApplicationNo. 400621 filed on 03/06/1995US Classes:360/51, Data clocking327/159, With digital element327/160, With counter331/25Signal or phase comparatorExaminersPrimary: Psitos, Aristotelis M.Assistant: Habermehl, James L Attorney, Agent or FirmInternational ClassG11B 027/32AbstractThe invention is a write clock generator circuit adapted for use in disk drives having either dedicated servo or sector servo architecture. A high frequency write clock signal is generated from a relatively low frequency reference signal synchronized to disk rotation. The reference signal may originate from a number of sources, including a dedicated servo pattern, a sector servo pattern, any index pattern, or a spindle pulse. A clock generates a clock signal having a predetermined number of cycles for each reference period. A counter coupled to the output of the clock counts the number of clock cycles generated for each reference period. The number of cycles is then compared to an expected number corresponding to a desired clock frequency. If the compared numbers are not the same, an error signal is generated. Control logic receives the error signal and the reference signal, and generates an appropriate control signal. The control signal is coupled to the clock and thereby adjusts the write clock signal frequency.Other References
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