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US Patent 5530832 - System and method for practicing essential inclusion in a multiprocessor and cache hierarchy
US Patent Issued on June 25, 1996
Estimated Patent Expiration Date:
October 14, 2013Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
Estimated Patent Expiration Date:
October 14, 2013Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.AbstractA system and method for managing caches in a multiprocessor having multiple levels of caches. An inclusion architecture and procedure are defined through which the L2 caches shield the L1 caches from extraneous communication at the L2, such as main memory and I/O read/write operations. Essential inclusion eliminates special communication from the L1 cache to the L2, yet maintains adequate knowledge at the L2, regarding the contents of the L1, to minimize L1 invalidations. Processor performance is improved by the reduced communication and the decreased number of invalidations. The processors and L1 caches practice a store-in policy. The L2 cache uses inclusion bits to designate by cache line a relationship between the line of data in the L2 cache and the corresponding lines as they exist in the associated L1 caches. Communication and invalidations are reduced through a selective setting/resetting of the inclusion bits and related L2 interrogation practice.Other References
| InventorsApplicationNo. 136631 filed on 10/14/1993US Classes:711/122, Hierarchical caches711/119, Multiple caches711/124, Cross-interrogating711/130Shared cacheExaminersPrimary: Rudolph, Rebecca L.Assistant: Nguyen, Hiep T. Attorney, Agent or FirmUS Patent References4774654, Apparatus and method for prefetching subblocks from a low speed memory to a high speed memory of a memory hierarchy depending upon state of replacing bit in the low speed memoryIssued on: 09/27/1988 Inventor: Pomerene , et al.4797814, Variable address mode cache Issued on: 01/10/1989 Inventor: Brenza4939641, Multi-processor system with cache memories Issued on: 07/03/1990 Inventor: Schwartz, et al.5023776, Store queue for a tightly coupled multiple processor configuration with two-level cache buffer storage Issued on: 06/11/1991 Inventor: Gregor5265232, Coherence control by data invalidation in selected processor caches without broadcasting to processor caches not having the data Issued on: 11/23/1993 Inventor: Gannon, et al.5269013, Adaptive memory management method for coupled memory multiprocessor systems Issued on: 12/07/1993 Inventor: Abramson, et al.5276848, Shared two level cache including apparatus for maintaining storage consistency Issued on: 01/04/1994 Inventor: Gallagher, et al.5307477, Two-level cache memory system Issued on: 04/26/1994 Inventor: Taylor, et al.5369753Method and apparatus for achieving multilevel inclusion in multilevel cache hierarchies Issued on: 11/29/1994 Inventor: Tipley Foreign Patent References
International ClassG06F 012/08 |
