U.S. patents available from 1976 to present.
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Manufacturing dual sided wire bonded integrated circuit chip packages using offset wire bonds and support block cavities

Patent 5527740 Issued on June 18, 1996. Estimated Expiration Date: Icon_subject June 28, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3533896

Method of manufacturing semiconductor devices using laser beam cutting
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Inventor: Tijburg ,   et al.

Process for the production of mutually electrically insulated monocrystalline silicon islands using laser recrystallization
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Method for separating monolithically produced laser diodes
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Process for the separation of monolithic LED chip arrangements generated on a semiconductor substrate wafer
Patent #: 4929300
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Inventor: Wegleiter

Method of assembling stacks of integrated circuit dies
Patent #: 4984358
Issued on: 01/15/1991
Inventor: Nelson, ;, , , --> Nelson

Double-die semiconductor package having a back-bonded die and a face-bonded die interconnected on a single leadframe
Patent #: 5012323
Issued on: 04/30/1991
Inventor: Farnworth

Wafer having a dicing area having a step region covered with a conductive layer and method of manufacturing the same
Patent #: 5017512
Issued on: 05/21/1991
Inventor: Takagi

Method of obtaining semiconductor chips
Patent #: 5024970
Issued on: 06/18/1991
Inventor: Mori

Semiconductor device package with dies mounted on both sides of the central pad of a metal frame
Patent #: 5034350
Issued on: 07/23/1991
Inventor: Marchisi

More ...

Inventors

Application

No. 267878 filed on 06/28/1994

US Classes:

29/827, Beam lead frame or beam lead device257/E23.052, Assembly of semiconductor devices on lead frame (EPO)438/107, Assembly of plural semiconductive substrates each possessing electrical device438/123Lead frame

Examiners

Primary: Picardat, Kevin M.

Attorney, Agent or Firm

Foreign Patent References

  • 58-155749 JP. 09/13/1983
  • 58130553 JP. 09/13/1983
  • 62-92456 JP. 04/13/1987
  • 3-277927 JP. 10/13/1991
  • 5121462 JP. 05/13/1993
  • 5343608 JP. 12/13/1993

International Class

H01L 021/60

Abstract

A method is disclosed for constructing a dual-sided chip package onto a leadframe having a die pad and a set of lead fingers corresponding to the die pad. Integrated circuit dies are disposed onto each side of the die pad while the leadframe is supported with support blocks having cavities that accept the integrated circuit dies and that support each lead finger and that provide clearance for stitch bonds of the previously formed wire bonds. Thereafter, a one step plastic mold is formed around each assembly comprising the dual integrated circuit dies, the die pads, and the wire bonds.

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