Multistandard video signal decoder
Patent 5521645 Issued on May 28, 1996. Estimated Expiration Date: 
May 3, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
May 3, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesDigital video signal processor with distortion correction Sampling clock reproducing device Arrangement for receiving numerical data, comprising a circuit for recognizing the start of packets Framing code windows repositioning apparatus and method for teletext decoder Apparatus for providing TV program information Patent #: 5343300 InventorAssigneeApplicationNo. 434020 filed on 05/03/1995US Classes:348/465, Data separation or detection348/476, During sync, blanking, or overscan348/478During vertical blankingExaminersPrimary: Kostak, Victor R.Assistant: Flynn, Nathan J. Attorney, Agent or FirmForeign Patent References
International ClassH04N 007/087Foreign Application Priority Data1992-10-08 JPAbstractA data decoding device capable of decoding plural kinds of data superimposed in a vertical blanking period of a video signal. The device comprises means for detecting the line number and the intraline position in the vertical blanking period from vertical and horizontal sync signals and generating a line signal extract pulse, a data signal extract pulse and a reference signal extract pulse; binary circuit means for converting the video signal into a binary signal; PLL means for producing a data extract clock signal in synchronism with a clock reference signal extracted on the basis of the line signal extract pulse and the reference signal extract pulse; memory means supplied with the data extract clock signal and the binary signal in response to the line signal extract pulse and the data signal extract pulse, and storing the data signal therein; and control means capable of designating a plurality of durations for generating the respective extract pulses and a plurality of frequency division ratios in the PLL means. In the device, the circuits are usable in common to achieve curtailment in the production cost.Other References
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