Construction of hierarchical networks through extension
February 4, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSorting unit for a switching node comprising a plurality of digital switching matrix networks for fast, asynchronous packet switching networks Method for expanding N×N three-stage switching network to 2N×2N three-stage switching network High-speed mesh connected local area network Method of expanding a three-stage regular switching array Inter-computer message routing system with each computer having separate routinng automata for each dimension of the network System for routing messages in a vertex symmetric network by using addresses formed from permutations of the transmission line indicees Interconnecting network Routing technique for a hierarchical interprocessor-communication network between massively-parallel processors Patent #: 5224100 InventorsApplicationNo. 193421 filed on 02/04/1994US Classes:370/351, PATHFINDING OR ROUTING340/2.1, Path selection370/535, Multiplexing combined with demultiplexing379/272Path selection or routingExaminersPrimary: Hsu, Alpus H.Attorney, Agent or FirmInternational ClassesG06F 013/00H04J 003/00 AbstractA switching network incorporates expander graphs such as multibutterflies but avoids the wiring complications resulting from the randomness of such graphs. The network includes metanodes, each having plural routers. Channels of multiple interconnections are connected between the metanodes according to an upper level expander graph. Interconnections within the channels are randomly connected. Interconnections on the channels may be time multiplexed and they may be dynamically assigned to routers within a metanode.Other References
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