Read and write data aligner and method
August 27, 2013. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesChannel data buffer apparatus for a digital data processing system Apparatus and method for providing byte and word compatible information transfers Logic control system for efficient memory to CPU transfers Byte addressable memory for variable length instructions and data Apparatus for storing and retrieving data in predetermined multi-bit quantities containing fewer bits of data than word length quantities Circuits for accessing a variable width data bus with a variable width data field Network interface module and method Dual byte order computer architecture a functional unit for handling data sets with differnt byte orders Data alignment correction apparatus for properly formatting data structures for different computer architectures Data-processing system having a packet transfer type input/output system InventorApplicationNo. 113417 filed on 08/27/1993US Classes:710/316Path selecting switchExaminersPrimary: Harvey, Jack B.Assistant: Chung-Trans, Xuong M. Attorney, Agent or FirmInternational ClassH01J 013/00AbstractA data aligner transfers data from an input having N+1 byte lanes to an output having N+1 byte lanes. The data aligner includes a write data aligner and a read data aligner. The write data aligner includes a write shifter coupled to the N input byte lanes and a stage having N selector/registers S1(i). The N selector/registers each have a queuing register R(i) and bypass multiplexer M(i). The N selector/registers are coupled to the N output byte lanes. The write shifter and N selector/registers S1(i) are coupled to a control circuit. The read data aligner includes a stage having N selector/registers S2(i) and a read shifter. The S2(i) selector/registers are coupled to N+1 byte input lanes with the S2(i) outputs coupled to the N read shifter inputs. The read shifter outputs are then coupled to the N+1 output byte lanes. Finally, a control circuit is coupled to the selector/registers S2(i) and read shifter. | |
