Patent References 3769607 Multiple clock selection system Automatic clock de-skewing apparatus Center frequency high resolution digital phase-lock loop circuit Apparatus and method for digital compensation of oscillator drift Method and apparatus for restoring data Clock distributor Integrated logic circuit with clock skew adjusters Clock signal supply system Method and apparatus for controlling clock skew InventorsAssigneeApplicationNo. 262921 filed on 06/21/1994US Classes:375/371, Phase displacement, slip or jitter correction327/144, Using multiple clocks327/262, Including significant compensation (e.g., temperature compensated delay, etc.)375/357, Synchronization failure prevention714/700Skew detection correctionExaminersPrimary: Chin, StephenAssistant: Bocure, Tesfaldet Attorney, Agent or FirmInternational ClassH04L 007/00AbstractIn a telecommunication system having multiple timing subsystems receiving and distributing redundant timing signals, there is provided a circuitry for aligning first and second redundant timing signals and switching therebetween. The circuitry includes a selecting and switching circuitry for receiving the first and second redundant timing signals and designating one of the redundant timing signals as ACTIVE and the other as INACTIVE, and providing the ACTIVE timing signal as an output timing reference signal. The selecting and switching circuitry further switching the ACTIVE and INACTIVE timing signal designation and output timing reference signal in response to detecting fault or a clock switching command. The ACTIVE timing signal is provided to a first delay path having a programmable delay value, which delays it and produces a first output timing signal. A second delay path receives the INACTIVE redundant timing signal and produces a second output timing signal. The circuitry further includes a phase detector which receives the ACTIVE and INACTIVE output timing signals and generates a status signal indicative of phase relationship therebetween. The circuitry further provides for temperature compensation which measures and compensates for an effect of temperature change on the delay paths.Field of SearchSynchronization failure preventionNetwork synchronizing more than two stations Phase displacement, slip or jitter correction With frequency detector and phase detector Diversity (frequency or time) Phase error or phase jitter By phase Comparison between plural inputs (e.g., phase angle indication, lead-lag discriminator, etc.) Monitoring (e.g., failure detection, etc.) Having specific delay in producing output waveform Including significant compensation (e.g., temperature compensated delay, etc.) With delay means Phase lock loop Delay line or capacitor storage element charged or discharged through or by a relaxation oscillator type circuit to form pulse Delay line or capacitor storage element charges or discharges through a tube to form pulse Circuit having only two stable states (i.e., bistable) Master-slave bistable latch Variable or adjustable Single output with variable or selectable delay Multiple outputs with plurality of delay intervals Single clock output with multiple inputs Compensation for variations in external physical values (e.g., temperature, etc.) Delay controlled switch (e.g., fixed, single time of delay control, etc.) With variable or multiple adjustable time of delay control (e.g., variable charge-discharge, on-delay/off-delay control, etc.) Using multiple clocks | |