U.S. patents available from 1976 to present.
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Apparatus and method for clock alignment and switching

Patent 5515403 Issued on May 7, 1996. Estimated Expiration Date: Icon_subject June 21, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3769607

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Center frequency high resolution digital phase-lock loop circuit
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Apparatus and method for digital compensation of oscillator drift
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Inventor: Azevedo ,   et al.

Method and apparatus for restoring data
Patent #: 5054038
Issued on: 10/01/1991
Inventor: Hedberg

Clock distributor
Patent #: 5065454
Issued on: 11/12/1991
Inventor: Binz, et al.

Integrated logic circuit with clock skew adjusters
Patent #: 5122679
Issued on: 06/16/1992
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Clock signal supply system
Patent #: 5184027
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Method and apparatus for controlling clock skew
Patent #: 5204559
Issued on: 04/20/1993
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Inventors

Assignee

Application

No. 262921 filed on 06/21/1994

US Classes:

375/371, Phase displacement, slip or jitter correction327/144, Using multiple clocks327/262, Including significant compensation (e.g., temperature compensated delay, etc.)375/357, Synchronization failure prevention714/700Skew detection correction

Examiners

Primary: Chin, Stephen
Assistant: Bocure, Tesfaldet

Attorney, Agent or Firm

International Class

H04L 007/00

Abstract

In a telecommunication system having multiple timing subsystems receiving and distributing redundant timing signals, there is provided a circuitry for aligning first and second redundant timing signals and switching therebetween. The circuitry includes a selecting and switching circuitry for receiving the first and second redundant timing signals and designating one of the redundant timing signals as ACTIVE and the other as INACTIVE, and providing the ACTIVE timing signal as an output timing reference signal. The selecting and switching circuitry further switching the ACTIVE and INACTIVE timing signal designation and output timing reference signal in response to detecting fault or a clock switching command. The ACTIVE timing signal is provided to a first delay path having a programmable delay value, which delays it and produces a first output timing signal. A second delay path receives the INACTIVE redundant timing signal and produces a second output timing signal. The circuitry further includes a phase detector which receives the ACTIVE and INACTIVE output timing signals and generates a status signal indicative of phase relationship therebetween. The circuitry further provides for temperature compensation which measures and compensates for an effect of temperature change on the delay paths.

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