Three dimensional FAMOS memory devices
Patent 5508544 Issued on April 16, 1996. Estimated Expiration Date: 
September 27, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
September 27, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesNon-volatile semiconductor memory device EEPROM with trench-isolated bitlines Vertical memory cell array and method of fabrication Electrically erasable and programmable semiconductor memory device with trench memory transistor and manufacturing method of the same Patent #: 5338953 InventorAssigneeApplicationNo. 313482 filed on 09/27/1994US Classes:257/316, With additional contacted control electrode257/321, With thin insulator region for charging or discharging floating electrode by quantum mechanical tunneling257/322, With charging or discharging by control voltage applied to source or drain region (e.g., by avalanche breakdown of drain junction)257/330Gate electrode in grooveExaminersPrimary: Limanek, Robert P.Attorney, Agent or FirmForeign Patent References
International ClassH01L 029/788AbstractMemory cell transistors are provided in which column structures (12a, 14a) are formed at the face of a semiconductor substrate (10). Floating gates (46) and control gates (52) are formed adjacent to the column structures (12a, 14a). The floating gates (46) and control gates (52) are insulatively disposed by gate oxide layer (42) and insulating layer (50). Source regions (36) are implanted in the semiconductor substrate. Drain regions (38) are also implanted in the column structures (12a, 14a).Field of SearchWith additional contacted control electrodeWith charging or discharging by control voltage applied to source or drain region (e.g., by avalanche breakdown of drain junction) With thin insulator region for charging or discharging floating electrode by quantum mechanical tunneling With floating gate electrode | |
