System for executing scalar instructions in parallel based on control bits appended by compounding decoder
June 7, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMachine for multiple instruction execution Parallel processing method and apparatus for increasing processing throughout by parallel processing low level instructions having natural concurrencies System with a multiport memory and N processing units for concurrently/individually executing 2N-multi-instruction-words at first/second transitions of a single clock cycle Pipelined data processor capable of performing instruction fetch stages of a plurality of instructions simultaneously Parallel processing device to operate with parallel execute instructions Parallel pipelined instruction processing system for very long instruction word Patent #: 5333280 InventorsApplicationNo. 488464 filed on 06/07/1995US Classes:712/208, INSTRUCTION DECODING (E.G., BY MICROINSTRUCTION, START ADDRESS GENERATOR, HARDWIRED)712/215, Simultaneous issuance of multiple instructions712/216DYNAMIC INSTRUCTION DEPENDENCY CHECKING, MONITORING OR CONFLICT RESOLUTIONExaminersPrimary: Kim, Kenneth S.Attorney, Agent or FirmInternational ClassG06F 009/38AbstractAn instruction processor system for decoding compound instructions created from a series of base instructions of a scalar machine, the processor generating a series of compound instructions with an instruction format text having appended control bits in the instruction format text enabling the execution of the compound instruction format text in said instruction processor with a compounding facility which fetches and decodes compound instructions which can be executed as compounded and single instructions by the arithmetic and logic units of the instruction processor while preserving intact the scalar execution of the base instructions of a scalar machine which were originally in storage. The system nullifies any execution of a member instruction unit of a compound instruction upon occurrence of possible conditions, such as branch, which would affect the correctness of recording results of execution of the member instruction unit portion based upon the interrelationship of member units of the compound instruction with other instructions. The resultant series of compounded instructions generally executes in a faster manner than the original format which is preserved due to the parallel nature of the compounded instruction stream which is executed. | |
