Memory cache with interlaced data and method of operation
Patent 5499204 Issued on March 12, 1996. Estimated Expiration Date: 
July 5, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
July 5, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesCache apparatus for enabling overlap of instruction fetch operations Apparatus for maintaining consistency of a cache memory with a primary memory Execution of storage-immediate and storage-storage instructions within cache buffer storage Patent #: 5313613 InventorsAssigneeApplicationNo. 270628 filed on 07/05/1994US Classes:365/49, ASSOCIATIVE MEMORIES365/189.02, Multiplexing365/230.01, ADDRESSING711/100, STORAGE ACCESSING AND CONTROL712/215Simultaneous issuance of multiple instructionsExaminersPrimary: Nelms, David C.Assistant: Hoang, Huan Attorney, Agent or FirmInternational ClassG11C 015/00AbstractA memory cache (14) has a plurality of cache lines (50) for storing a series of contiguous memory elements. Each series of memory elements are interlaced within the corresponding cache line on a element-by-element basis and on a bit-by-bit basis. This storage strategy allows the memory cache to output a subset memory elements within a cache line quickly and in the original contiguous order. The invention may be advantageously incorporated in an instruction cache of superscalar data processor to provide a series of sequential instructions for execution. | |
