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Digitally self-calibrating pipeline analog-to-digital converter

Patent 5499027 Issued on March 12, 1996. Estimated Expiration Date: Icon_subject February 24, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Analog-to-digital converter using absolute-value conversion
Patent #: 4593268
Issued on: 06/03/1986
Inventor: Blauschild

Analog-digital converter
Patent #: 4691190
Issued on: 09/01/1987
Inventor: Robinson

Self-calibrating pipelined subranging analog-to-digital converter
Patent #: 4894656
Issued on: 01/16/1990
Inventor: Hwang, et al.

Architecture for high sampling rate, high resolution analog-to-digital converter system
Patent #: 4903026
Issued on: 02/20/1990
Inventor: Tiemann, et al.

Digital error correction system for subranging analog-to-digital converters
Patent #: 5047772
Issued on: 09/10/1991
Inventor: Ribner

Pipelined A/D converter
Patent #: 5274377
Issued on: 12/28/1993
Inventor: Matsuura, et al.

High-speed A/D conversion using a series of one-bit conversion stages
Patent #: 5283583
Issued on: 02/01/1994
Inventor: Ichihara

Accuracy bootstrapping
Patent #: 5327129
Issued on: 07/05/1994
Inventor: Soenen, et al.

Analog-to-digital conversion circuit with improved differential linearity Patent #: 5416485
Issued on: 05/16/1995
Inventor: Lee

Inventors

Application

No. 201250 filed on 02/24/1994

US Classes:

341/120, CONVERTER CALIBRATION OR TESTING341/162Serial conversions with change in signal

Examiners

Primary: Hoff, Marc S.

Attorney, Agent or Firm

International Class

H03M 001/10

Abstract

A self-calibrating pipeline analog-to-digital converter having a plurality of analog-to-digital conversion units and including a recursive calibrating section operable for calibrating errors associated with an immediately preceding first conversion unit. The recursive calibrating section includes circuitry for receiving an analog output signal generated from said first conversion unit in response to an analog input signal provided to the first conversion unit; circuitry for receiving a digital output signal generated from the first conversion unit in response to a digital input signal provided to the first conversion unit; circuitry for generating a conversion signal corresponding to a quantized representation of the analog output signal; and circuitry for generating a calibration signal having a value equal to the conversion signal in response to the digital input signal being a first digital value and having a value equal to the sum of the conversion signal and a calibration value in response to the digital input signal being a second digital value.

Other References

  • Soenen, Eric, "Error Modeling, Self-Calibration And Design Of Pipelined Analog To Digital Converters"; UMI Dissertation Services, vols. 1 and 2
  • Soenen, Eric G. and Geiger, Randall L., "An Architecture and An Algorithm for Fully Digital Correction of Monolithic Pipelined ADC's"; IEE Transactions On Circuits and Systems-II: Analog and Digital Signal Processing, vol. 42, No. 3, Mar. 1995, pp. 143-153
  • Soenen, Eric G. and Geiger, Randall L., "A Fully Digital Self-Calibration Method For High Resolution, Pipelined A/D Converters"; IEE 36the Midwest Symposium On Circuits And Systems. Aug. 16-18, 199
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