Parallel buffer/driver configuration between data sending terminal and data receiving terminal
December 13, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesAsynchronous status interlock circuit for interface adaptor Data transfer circuit Method and network for improving transmission of data signals between integrated circuit chips Assist circuit for a data bus in a data processing system Assist circuit for improving the rise time of an electronic signal Four-state I/O control circuit Level clamp for Tri-state CMOS bus structure High speed low pin count bus interface CMOS logic circuit Buffered routing element for a user programmable logic device InventorAssigneeApplicationNo. 355420 filed on 12/13/1994US Classes:326/30, Bus or line termination (e.g., clamping, impedance matching, etc.)326/82Current driving (e.g., fan in/out, off chip driving, etc.)ExaminersPrimary: Nelms, David C.Assistant: Dinh, Son T. Attorney, Agent or FirmInternational ClassH03K 017/16AbstractA buffer/driver is arranged in parallel between the data sending terminal and the data receiving terminal of a data transmission system. The SETUP time and HOLD time requirements of the data receiving terminal may be satisfied at the same time in accordance with the present invention. A low end, which has medium amount of time delay, buffer/driver may be used in this present invention to achieve a high performance of the data transmission which is usually possible in the past through the utilization of a high end buffer/driver, which has extremely small amount of time delay. | |
