Differential carry-save adder and multiplier
October 6, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesPrecharge arithmetic logic unit Dynamic logic circuits operating in a differential mode for array processing Clocked differential cascode voltage switch logic systems Logic operation circuit having an exclusive-OR circuit Full adder circuit using differential transistor pairs High-speed multiplier having carry-save adder circuit Intermediate frequency amplification circuit capable of detecting a field strength with low electric power High-speed dynamic domino circuit implemented with gaas mesfets Arithmetic operation circuit High speed digital computer data transfer system having reduced bus state transition time InventorsApplicationNo. 318924 filed on 10/06/1994US Classes:708/708, Carry-save adders708/625, Binary708/702, Field-Effect transistor (FET)708/704For precharging (e.g., Manchester, etc.)ExaminersPrimary: Mai, Tan V.Attorney, Agent or FirmInternational ClassesG06F 007/50G06F 007/52 AbstractA Carry-Save Adder circuit having differential signal response and output is provided. The circuit includes a pair of cross-coupled transistors powered by an upper voltage rail. The output of a first transistor of the pair of cross-coupled transistors is connected to the output of a first precharge transistor that is powered by the upper rail and controlled by a clock. The output of a second transistor of the pair of cross-coupled transistors is connected to the output of a second precharge transistor that is powered by the upper rail and controlled by the clock. A logic circuit is wired to perform a logical function, either a Sum or a Carry function, and has a plurality of inputs, an output, and a complementary output. The output of the logic circuit is connected to the output of the first transistor of the pair of cross-coupled transistors, and the complementary output is connected to the output of the second transistor of the pair of cross-coupled transistors. An enable transistor having a first terminal connected to a lower voltage rail, and being controlled by the complement of the clock, has a second terminal connected to the logic circuit such that the logic circuit is connected to the lower voltage rail through the enable transistor. | |
