Method of die burn-in
January 9, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMulti-function LSI wafers Wafer level integration technique Process of forming input/output wiring areas for semiconductor integrated circuit Semiconductor integrated circuit configured by using polycell technique Wafer-level burn-in testing of integrated circuits Making and testing an integrated circuit using high density probe points Method for manufacturing a semiconductor device including wafer aging, probe inspection, and feeding back the results of the inspection to the device fabrication process Patent #: 5219765 InventorsAssigneeApplicationNo. 370565 filed on 01/09/1995US Classes:438/15, Packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor438/106, PACKAGING (E.G., WITH MOUNTING, ENCAPSULATING, ETC.) OR TREATMENT OF PACKAGED SEMICONDUCTOR438/107, Assembly of plural semiconductive substrates each possessing electrical device438/113Substrate dicingExaminersPrimary: Chaudhuri, OlikAssistant: Tsai, H. Jey Foreign Patent References
International ClassesG01R 031/26H01L 021/66 AbstractThe present invention provides for a burn-in test which is conducted on the wafer level, before the dies are separated into individual chips and packaged. In a preferred embodiment of the invention, a series of chips are each connected to an external current, ground, and/or alternate signal source(s) for burn-in. Generally, the method herein for a burn-in of a semiconductor die comprises the step of: (a) providing an electrical connection between a die on a semiconductor wafer and an external current source; (b) heating the semiconductor wafer; and (c) applying a common signal across the electrical connection to burn in the die. A preferred method herein provides a semiconductor wafer including a multiplicity of dies and wafer level test points, at least one layer of conductive lines overlying the semiconductor wafer, a means for connecting an individual conductive line to a test point on the wafer; and a means for connecting the conductive lines to an external signal source for exercising the dies. | |
