Method and apparatus for field testing field programmable logic arrays
October 4, 2013. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesOn chip test system for configurable gate arrays Built in self test input generator for programmable logic arrays Programmable logic array In-system programmable logic device CMOS implementation of a built-in self test input generator (BISTIG) Method and circuitry for enabling internal test operations in a VLSI chip Debug routine accessing system Memory testing device Self-testing circuitry for VLSI units Method and apparatus for program verification of a field programmable logic device InventorAssigneeApplicationNo. 131070 filed on 10/04/1993US Classes:714/725, Programmable logic array (PLA) testing714/724Digital logic testingExaminersPrimary: Voeltz, Emanuel T.Assistant: Pipala, Edward Attorney, Agent or FirmForeign Patent References
International ClassG06F 011/00AbstractDisclosed are methods and apparatus for a testing a field programmable logic gate array. In the method the non-volatile gates are set to a testable setting. The programmable logic array is then configured into (1) a pseudo random pattern generator, (2) a multiple input signature register, (3) a signature comparator, and (4) AND-plane and OR-plane logic array areas. A pseudo random set of test pattern vectors is applied to the programmable logic array from the pseudo random pattern generator. The output is captured in the multiple input signature register and compared in the comparator. Finally, individual non-volatile floating gate field effect transistors are selectively set to provide the desired set of sums of products. | |
