Patent ReferencesData caching and address translation system with rapid turnover cycle Method for releasing space in flash EEPROM memory array to allow the storage of compressed data Method for writing to a flash memory array during erase suspend intervals Block specific status information in a memory device Method for detaching sectors in a flash EEPROM memory array Flash file system Patent #: 5404485 InventorsAssigneeApplicationNo. 131495 filed on 10/04/1993US Classes:711/103, Programmable read only memory (PROM, EEPROM, etc.)365/185.11, Bank or block architecture711/104, Solid-state random access memory (RAM)711/108, Content addressable memory (CAM)711/156, Status storage711/203Virtual addressingExaminersPrimary: Gossage, GlennAssistant: Bragdon, Reginald G. Attorney, Agent or FirmInternational ClassesG06F 012/02G06F 012/14 AbstractA semiconductor mass storage device can be substituted for a rotating hard disk. The device avoid an erase cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. Secondly, a circuit and method are provided for evenly using all blocks in the mass storage. These advantages are achieved through the use of several flags, a map to correlate a logical address of a block to a physical address of that block and a count register for each block. In particular, flags are provided for defective blocks, used blocks, old versions of a block, a count to determine the number of times a block has been erased and written and an erase inhibit flag. Reading is performed by providing the logical block address to the memory storage. The system sequentially compares the stored logical block addresses until it finds a match. That data file is then coupled to the system. | |