Static-random-access memory cell and an integrated circuit having a static-random-access memory cell
July 21, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod of manufacture for self-aligned floating gate memory cell Semiconductor memory device Semiconductor memory device MOS static ram with capacitively loaded gates to prevent alpha soft errors MOS/CMOS memory cell Random access memory cell resistant to inadvertant change of state due to charged particles Self-aligned sidewall gate IGFET Stacked static random access memory cell having capacitor High impendance-coupled CMOS SRAM for improved single event immunity Static random access memory with reduced soft error rate InventorsAssigneeApplicationNo. 278465 filed on 07/21/1994US Classes:365/154, Flip-flop (electrical)257/277, With capacitive or inductive elements257/303, Stacked capacitor257/903, FET CONFIGURATION ADAPTED FOR USE AS STATIC MEMORY CELL257/E21.661, Static random access memory structures (SRAM) (EPO)365/149CapacitorsExaminersPrimary: Nelms, David C.Assistant: Niranjan, F. Attorney, Agent or FirmForeign Patent References
International ClassG11C 011/00AbstractThe present invention includes an integrated circuit having a self-aligned contact that makes contact to both a region within the substrate and a capacitor plate of a capacitor that is adjacent to the doped region. The present invention also includes a static-random-access memory cell with a capacitor having a first plate and a second plate. The first plate includes a first plate section of a gate electrode of a transistor, and the second plate includes a first conductive member that is substantially coincident with the first plate section. The second plate may be formed over a gate electrode of a latch transistor or over a word line. The disclosure includes methods of forming the integrated circuit and the static-random-access memory cell.Other References
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