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US Patent 5485420 - Static-random-access memory cell and an integrated circuit having a static-random-access memory cell

US Patent Issued on January 16, 1996
Estimated Patent Expiration Date: Icon_subject July 21, 2014Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
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Abstract

The present invention includes an integrated circuit having a self-aligned contact that makes contact to both a region within the substrate and a capacitor plate of a capacitor that is adjacent to the doped region. The present invention also includes a static-random-access memory cell with a capacitor having a first plate and a second plate. The first plate includes a first plate section of a gate electrode of a transistor, and the second plate includes a first conductive member that is substantially coincident with the first plate section. The second plate may be formed over a gate electrode of a latch transistor or over a word line. The disclosure includes methods of forming the integrated circuit and the static-random-access memory cell.

Other References

  • Wang; "High Performance, High Density Capacitively Loaded FET Static RAM"; IBM Tech. Discl. Bulletin; vol. 27, No. 4A; pp. 1950-1951 (1984)
  • Yamanaka et al.; "A 25 μm2, New Poly-Si PMOS Load (PPL) SRAM Cell Having Excellent Soft Error Immunity"; IEDM; pp. 48-51 (1988)
  • Itabashi, et al.; "A Split Wordline Cell for 16 Mb SRAM Using Polysilicon Sidewall Contacts"; IEDM; pp. 477-480 (1991)
  • Chappell, et al.; "Stability and SER Analysis of Static RAM Cells;" IEEE Trans. on Electron Dev.; vol. ED-32, No. 2; pp. 463-470 (1985

Inventors

Assignee

Application

No. 278465 filed on 07/21/1994

US Classes:

365/154, Flip-flop (electrical)257/277, With capacitive or inductive elements257/303, Stacked capacitor257/903, FET CONFIGURATION ADAPTED FOR USE AS STATIC MEMORY CELL257/E21.661, Static random access memory structures (SRAM) (EPO)365/149Capacitors

Field of Search

365/154, Flip-flop (electrical)365/149, Capacitors365/182, Insulated gate devices257/277, With capacitive or inductive elements257/303, Stacked capacitor257/903FET CONFIGURATION ADAPTED FOR USE AS STATIC MEMORY CELL

Examiners

Primary: Nelms, David C.
Assistant: Niranjan, F.

Attorney, Agent or Firm

US Patent References

4355455, Method of manufacture for self-aligned floating gate memory cell
Issued on: 10/26/1982
Inventor: Boettcher
4532609, Semiconductor memory device
Issued on: 07/30/1985
Inventor: Iizuka
4535426, Semiconductor memory device
Issued on: 08/13/1985
Inventor: Ariizumi ,   et al.
4590508, MOS static ram with capacitively loaded gates to prevent alpha soft errors
Issued on: 05/20/1986
Inventor: Hirakawa ,   et al.
4679171, MOS/CMOS memory cell
Issued on: 07/07/1987
Inventor: Logwood ,   et al.
4725981, Random access memory cell resistant to inadvertant change of state due to charged particles
Issued on: 02/16/1988
Inventor: Rutledge
4729002, Self-aligned sidewall gate IGFET
Issued on: 03/01/1988
Inventor: Yamazaki
4805147, Stacked static random access memory cell having capacitor
Issued on: 02/14/1989
Inventor: Yamanaka ,   et al.
4805148, High impendance-coupled CMOS SRAM for improved single event immunity
Issued on: 02/14/1989
Inventor: Diehl-Nagle ,   et al.
4879690, Static random access memory with reduced soft error rate
Issued on: 11/07/1989
Inventor: Anami, et al.
5073510, Fabrication method of contact window in semiconductor device
Issued on: 12/17/1991
Inventor: Kwon, et al.
5132771, Semiconductor memory device having flip-flop circuits
Issued on: 07/21/1992
Inventor: Yamanaka, et al.
5135881, Method of making random access memory device having memory cells each implemented by a stacked storage capacitor and a transfer transistor with lightly-doped drain structure
Issued on: 08/04/1992
Inventor: Saeki
5145799, Stacked capacitor SRAM cell
Issued on: 09/08/1992
Inventor: Rodder
5240872, Method of manufacturing semiconductor device having interconnection layer contacting source/drain regions
Issued on: 08/31/1993
Inventor: Motonami, et al.
5264391Method of forming a self-aligned contact utilizing a polysilicon layer
Issued on: 11/23/1993
Inventor: Son, et al.

Foreign Patent References

  • 0475688 EP. 03/09/1992

International Class

G11C 011/00

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