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Static-random-access memory cell and an integrated circuit having a static-random-access memory cell

Patent 5485420 Issued on January 16, 1996. Estimated Expiration Date: Icon_subject July 21, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Method of manufacture for self-aligned floating gate memory cell
Patent #: 4355455
Issued on: 10/26/1982
Inventor: Boettcher

Semiconductor memory device
Patent #: 4532609
Issued on: 07/30/1985
Inventor: Iizuka

Semiconductor memory device
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Issued on: 08/13/1985
Inventor: Ariizumi ,   et al.

MOS static ram with capacitively loaded gates to prevent alpha soft errors
Patent #: 4590508
Issued on: 05/20/1986
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MOS/CMOS memory cell
Patent #: 4679171
Issued on: 07/07/1987
Inventor: Logwood ,   et al.

Random access memory cell resistant to inadvertant change of state due to charged particles
Patent #: 4725981
Issued on: 02/16/1988
Inventor: Rutledge

Self-aligned sidewall gate IGFET
Patent #: 4729002
Issued on: 03/01/1988
Inventor: Yamazaki

Stacked static random access memory cell having capacitor
Patent #: 4805147
Issued on: 02/14/1989
Inventor: Yamanaka ,   et al.

High impendance-coupled CMOS SRAM for improved single event immunity
Patent #: 4805148
Issued on: 02/14/1989
Inventor: Diehl-Nagle ,   et al.

Static random access memory with reduced soft error rate
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Issued on: 11/07/1989
Inventor: Anami, et al.

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Inventors

Assignee

Application

No. 278465 filed on 07/21/1994

US Classes:

365/154, Flip-flop (electrical)257/277, With capacitive or inductive elements257/303, Stacked capacitor257/903, FET CONFIGURATION ADAPTED FOR USE AS STATIC MEMORY CELL257/E21.661, Static random access memory structures (SRAM) (EPO)365/149Capacitors

Examiners

Primary: Nelms, David C.
Assistant: Niranjan, F.

Attorney, Agent or Firm

Foreign Patent References

  • 0475688 EP. 03/11/1992

International Class

G11C 011/00

Abstract

The present invention includes an integrated circuit having a self-aligned contact that makes contact to both a region within the substrate and a capacitor plate of a capacitor that is adjacent to the doped region. The present invention also includes a static-random-access memory cell with a capacitor having a first plate and a second plate. The first plate includes a first plate section of a gate electrode of a transistor, and the second plate includes a first conductive member that is substantially coincident with the first plate section. The second plate may be formed over a gate electrode of a latch transistor or over a word line. The disclosure includes methods of forming the integrated circuit and the static-random-access memory cell.

Other References

  • Wang; "High Performance, High Density Capacitively Loaded FET Static RAM"; IBM Tech. Discl. Bulletin; vol. 27, No. 4A; pp. 1950-1951 (1984)
  • Yamanaka et al.; "A 25 μm2, New Poly-Si PMOS Load (PPL) SRAM Cell Having Excellent Soft Error Immunity"; IEDM; pp. 48-51 (1988)
  • Itabashi, et al.; "A Split Wordline Cell for 16 Mb SRAM Using Polysilicon Sidewall Contacts"; IEDM; pp. 477-480 (1991)
  • Chappell, et al.; "Stability and SER Analysis of Static RAM Cells;" IEEE Trans. on Electron Dev.; vol. ED-32, No. 2; pp. 463-470 (1985
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