ECL to CMOS converter
April 5, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesLogic circuit utilizing a current switch circuit having a non-threshold transfer characteristic ECL to CMOS transition amplifier Semiconductor circuit with low power consumption having emitter-coupled logic or differential amplifier BiCMOS inverter circuit Apparatus and method for translating ECL signals to CMOS signals Level shift circuit for achieving a high-speed processing and an improved output current capability Level-shifter circuit for high-speed low-power BiCMOS ECL to CMOS input buffers BICMOS level converter circuit Patent #: 5315179 InventorsApplicationNo. 222988 filed on 04/05/1994US Classes:326/66, ECL to/from CMOS326/18, Bipolar transistor326/85, Having plural output pull-up or pull-down transistors326/110Bi-CMOSExaminersPrimary: Westin, Edward P.Assistant: Santamauro, Jon Attorney, Agent or FirmInternational ClassesH03K 019/017.5H03K 019/082 H03K 019/094.8 AbstractAn efficient high-speed ECL to CMOS logic converter for BiCMOS integrated circuits. In one embodiment, a differential amplifier compares an ECL input signal to an ECL reference voltage and generates a pair of complementary intermediate signals on a corresponding pair of differential output nodes. The differential amplifier has two load resistors coupled in series with a common load resistor which limits the upper voltage swing at the differential output nodes. A regenerative stage coupled to the differential output nodes switches between a partially on state and a fully on state in response to the complementary intermediate signals. A pair of inverter stages convert the complementary intermediate signals into a pair of CMOS level signals. A pair of complementary output drivers coupled to the respective complementary inverter stages provide current driving capability. In this embodiment, each output driver includes a CMOS inverter pair and a bipolar transistor coupled between the respective output node of the driver and VDD.Other References
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