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Gettering of unwanted metal impurity introduced into semiconductor substrate during trench formation

Patent 5482869 Issued on January 9, 1996. Estimated Expiration Date: Icon_subject March 1, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

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Inventor

Assignee

Application

No. 203943 filed on 03/01/1994

US Classes:

438/476, By layers which are coated, contacted, or diffused257/913, WITH MEANS TO ABSORB OR LOCALIZE UNWANTED IMPURITIES OR DEFECTS FROM SEMICONDUCTORS (E.G., HEAVY METAL GETTERING)257/E21.318, Of silicon body, e.g., for gettering (EPO)257/E21.396, Metal-insulator-semiconductor capacitor, e.g., trench capacitor (EPO)257/E21.549, Of trenches having shape other than rectangular or V shape, e.g., rounded corners, oblique or rounded trench walls (EPO)438/386Trench capacitor

Examiners

Primary: Chaudhuri, Olik
Assistant: Mulpuri, S.

Attorney, Agent or Firm

Foreign Patent References

  • 58-138035 JP 08/13/1983
  • 62-208638 JP 09/13/1987
  • 2-12920 JP 01/13/1990

International Class

H01L 021/306

Foreign Application Priority Data

1993-03-01 JP

Abstract

After a trench is formed in a semiconductor substrate, a semiconductor film is formed on the inner wall of the trench. Annealing is performed in a predetermined condition to subject an unwanted metal impurity to gettering into the semiconductor film. The semiconductor film is then oxidized.

Other References

  • IEEE Transactions on Electron Devices, vol. 35, No. 8, Aug. 1988, pp. 1257-1263; "Half-Vcc Sheath-Plate Capacitor DRAM Cell with Self-Aligned Buried Plate Wiring
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