Patent ReferencesMethod of making an isolation slot for integrated circuit structure Solubilization chromatography Fabrication method for forming a self-aligned contact window and connection in an epitaxial layer and device structures employing the method Post dry-etch cleaning method for restoring wafer properties Method of manufacturing a semiconductor device by mega-electron volt ion implantation Method of making trench type dynamic random access memory device Method to getter contamination in semiconductor devices Method of making contact electrodes of polysilicon in semiconductor device Method of manufacturing a semiconductor device Patent #: 5360748 InventorAssigneeApplicationNo. 203943 filed on 03/01/1994US Classes:438/476, By layers which are coated, contacted, or diffused257/913, WITH MEANS TO ABSORB OR LOCALIZE UNWANTED IMPURITIES OR DEFECTS FROM SEMICONDUCTORS (E.G., HEAVY METAL GETTERING)257/E21.318, Of silicon body, e.g., for gettering (EPO)257/E21.396, Metal-insulator-semiconductor capacitor, e.g., trench capacitor (EPO)257/E21.549, Of trenches having shape other than rectangular or V shape, e.g., rounded corners, oblique or rounded trench walls (EPO)438/386Trench capacitorExaminersPrimary: Chaudhuri, OlikAssistant: Mulpuri, S. Attorney, Agent or FirmForeign Patent References
International ClassH01L 021/306Foreign Application Priority Data1993-03-01 JPAbstractAfter a trench is formed in a semiconductor substrate, a semiconductor film is formed on the inner wall of the trench. Annealing is performed in a predetermined condition to subject an unwanted metal impurity to gettering into the semiconductor film. The semiconductor film is then oxidized.Other References
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