Method for restoring a prescribed sequence for unordered cell streams in ATM switching technology

Patent 5481536 Issued on January 2, 1996. Estimated Expiration Date:

September 9, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

Resequencing system for a switching node
Patent #: 5127000
Issued on: 06/30/1992
Inventor: Henrion

Switching system with time-stamped packet distribution input stage and packet sequencing output stage
Patent #: 5253251
Issued on: 10/12/1993
Inventor: Aramaki

Method and system for managing queued cells
Patent #: 5278828
Issued on: 01/11/1994
Inventor: Chao

Threshold-based load balancing in ATM switches with parallel switch planes related applications
Patent #: 5355372
Issued on: 10/11/1994
Inventor: Sengupta, et al.

Method and system for controlling user traffic to a fast packet switching system Patent #: 5381407
Issued on: 01/10/1995
Inventor: Chao

Inventors

Assignee

Siemens Aktiengesellschaft

Application

No. 303837 filed on 09/09/1994

US Classes:

370/394, Sequencing or resequencing of packets to insure proper output sequence order370/395.7Having detail of switch memory reading/writing

Examiners

Primary: Olms, Douglas W.
Assistant: Jung, Min

Attorney, Agent or Firm

Hill, Steadman & Simpson

International Class

H04J 003/26

Foreign Application Priority Data

1993-10-29 DE

Abstract

In the method a generally unordered cell stream (ICS) is supplied to a generally centrally administered cell memory (CM) and is intermediately stored therein. Path identifier/sequence number signals (VPI/SN) are derived from the cells of the supplied cell stream and are supplied to a resequencing controller (RC) wherein addresses (ADR) for addressing the cell memory (CM) are formed such that an ordered cell stream (OOCS) arises at the output of the cell memory. The method is used in ATM switching technology for switching networks wherein cells of a connection traverse the switching network with different running times.