Resequencing system for a switching node
Switching system with time-stamped packet distribution input stage and packet sequencing output stage
Method and system for managing queued cells
Threshold-based load balancing in ATM switches with parallel switch planes related applications
Method and system for controlling user traffic to a fast packet switching system Patent #: 5381407
ApplicationNo. 303837 filed on 09/09/1994
US Classes:370/394, Sequencing or resequencing of packets to insure proper output sequence order370/395.7Having detail of switch memory reading/writing
ExaminersPrimary: Olms, Douglas W.
Assistant: Jung, Min
Attorney, Agent or Firm
International ClassH04J 003/26
Foreign Application Priority Data1993-10-29 DE
AbstractIn the method a generally unordered cell stream (ICS) is supplied to a generally centrally administered cell memory (CM) and is intermediately stored therein. Path identifier/sequence number signals (VPI/SN) are derived from the cells of the supplied cell stream and are supplied to a resequencing controller (RC) wherein addresses (ADR) for addressing the cell memory (CM) are formed such that an ordered cell stream (OOCS) arises at the output of the cell memory. The method is used in ATM switching technology for switching networks wherein cells of a connection traverse the switching network with different running times.