Single cycle dispatch delay in a multiple instruction dispatch mechanism of a data processing system
Patent 5479622 Issued on December 26, 1995. Estimated Expiration Date: November 14, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
A data processing system including a circuit for storing a plurality of instructions in a sequence together with a circuit for fetching a plurality of instructions. A circuit is provided for dispatching a plurality of the instructions to one or more processors for execution during a single computation cycle. A control circuit is connected to the dispatching circuit to delay the dispatching of an instruction. when the instruction has an execution result that is dependent upon a previous instruction execution that will set at least one bit in a condition register. The delayed instruction is delayed until that condition register has been accordingly set.
Other References
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November 14, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
