Carrier tape including molten resin flow path element for resin packaged semiconductor devices
Method for electroplating the lead pins of a semiconductor device pin grid array package
Semiconductor chip assemblies with fan-in leads
Process for manufacturing a multilayer integrated circuit interconnection
Semiconductor chip assemblies and methods of making same
Method of making an electronic assembly having a flexible circuit wrapped around a substrate
Method for making high pin count package for semiconductor device
Process for assembling a TAB grid array package for an integrated circuit Patent #: 5409865
ApplicationNo. 430590 filed on 04/28/1995
US Classes:29/827, Beam lead frame or beam lead device29/840, By metal fusion257/E23.055, Consisting of thin flexible metallic tape with or without film carrier (EPO)257/E23.069, Spherical bumps on substrate for external connection, e.g., ball grid arrays (BGA) (EPO)257/E23.133, Coating also covering sidewalls of semiconductor body (EPO)438/122, Possessing thermal dissipation structure (i.e., heat sink)438/123, Lead frame438/125Insulative housing or support
ExaminersPrimary: Picardat, Kevin M.
International ClassH01L 021/60
Foreign Application Priority Data1994-05-09 JP
AbstractConductive leads are connected at inner ends thereof to electrodes of a semiconductor chip through a tape automated bonding process, and bumps are formed on the other ends of the conductive leads so as to economically and reliably mount the semiconductor chip on a circuit board through a concurrent reflow.