Flash EEPROM array data and header file structure

Patent 5471478 Issued on November 28, 1995. Estimated Expiration Date:

March 10, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

Circuit for controlling a flash EEPROM having three distinct modes of operation by allowing multiple functionality of a single pin
Patent #: 4970692
Issued on: 11/13/1990
Inventor: Ali, et al.

Device and method for defect handling in semi-conductor memory
Patent #: 5200959
Issued on: 04/06/1993
Inventor: Gross, et al.

Flash EEPROM system and intelligent programming and erasing methods therefor
Patent #: 5268870
Issued on: 12/07/1993
Inventor: Harari

Method for optimum erasing of EEPROM
Patent #: 5270979
Issued on: 12/14/1993
Inventor: Harari, et al.

Flash eeprom system Patent #: 5297148
Issued on: 03/22/1994
Inventor: Harari, et al.

Inventors

Assignee

Application

No. 401942 filed on 03/10/1995

US Classes:

714/711, Spare row or column365/200, Bad bit714/710Replacement of memory spare location, portion, or segment

Examiners

Primary: Canney, Vincent P.

Attorney, Agent or Firm

Majestic, Parsons, Siebert & Hsue

Foreign Patent References

392895 EP. 02/13/1990

International Class

G06F 011/00

Abstract

A file structure employed in a flash electrically erasable and programmable read only memory ("EEPROM") system and aspects of forming and using certain data fields within such a file structure. An array of rows and columns of EEPROM memory cells is divided into blocks of cells that are separately addressable for the purpose of erasing an entire block of cells at the same time. Each block contains several rows of cells with certain columns thereof storing a sector of data, typically 512 bytes of data, and other columns of cells within the same rows being used as spare cells to replace any defective sector data cells and store overhead (header) information about the block and the data sector. Such overhead information includes pointers to locations of any defective sector data cells within the block, whether the block has been mapped out in favor of another block, error correction codes for the sector data and the header information, and other similar types of information.

Other References

Lai, "Writing MSDOS.RTM. Device Drivers," The Waite Group, Second Edition, pp. 475-479
Lai, "Writing MSDOS.RTM. Device Drivers," The Waite Group, Second Edition, pp. 275-280
Bartee, "Digital Computer Fundamentals," McGraw-Hill, Inc., Sixth Edition, pp. 263-265
Short, "Microprocessors & Programmed Logic," Prentice-Hall, Inc., (1987) pp. 492-495 and 514-51