Fast adder chain

Patent 5471413 Issued on November 28, 1995. Estimated Expiration Date:

May 25, 2013. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

High speed NXM bit digital, repeated addition type multiplying circuit
Patent #: 4369500
Issued on: 01/18/1983
Inventor: Fette

Pyramid carry adder circuit
Patent #: 4660165
Issued on: 04/21/1987
Inventor: Masumoto

Binary MOS ripple-carry parallel adder/subtracter and adder/subtracter stage suitable therefor
Patent #: 4683548
Issued on: 07/28/1987
Inventor: Mlynek

Binary adding apparatus
Patent #: 5036483
Issued on: 07/30/1991
Inventor: Virtue

High speed full adder and method Patent #: 5175703
Issued on: 12/29/1992
Inventor: Ong

Inventors

Assignee

SGS-Thomson Microelectronics S.A.

Application

No. 066567 filed on 05/25/1993

US Classes:

708/706Parallel

Examiners

Primary: Malzahn, David H.

Attorney, Agent or Firm

Wolf, Greenfield & Sacks

Foreign Patent References

0391516 EP. 10/13/1990

International Class

G06F 007/52

Foreign Application Priority Data

1992-05-27 EP

Abstract

A fast adder chain for adding together at least one pair of digital words and including a plurality of cascade connected adder blocks. Each block including adders for obtaining the pseudosum of portions of the digital word pair and latches for storing and transmitting the pseudosum to the next block and the pseudocarry from each adder to the chain end.

Other References

IBM Technical Disclosure Bulletin, vol. 17, No. 1, Jun. 1974, New York, U.S., pp. 118-119, J. Beraud, "High-Speed Accumulator"
Proceedings of the 1990 IEEE International Symposium on Circuits and Systems, 1-3 May, 1990, New Orleans, La., USA, vol. 2, IEEE, New York, USA, pp. 982-986, T. Noll, "Carry-Save Arithmetic for High-Speed Digital Signal Processing"
Computer Journal, vol. 29, No. 6, Dec. 1986, London, GB, pp. 495-499, W. Clocksin, "Automatic Specialisation of Standard Design"
K. Hwang, "Computer Arithmetic", 1979, J. Wiley & Sons, New York, U.S., pp. 40-43
IEE Proceedings G. Electronic Circuits & Systems, vol. 133, No. 5 Oct. 1986, Stevenage GB pp. 256-264, H. Yung et al., "Recursive addition and its parameterisation in VLSI"
IEEE Journal of Solid-State Circuits, vol. 23, No. 2, Apr., 1988 New York U.S. pp. 573-580, C. Ekroot "A GaAs 4-bit Adder-Accumulator Circuit for Direct Digital Synthesis