Input/output pin assignment method
Comparison and verification system for logic circuits and method thereof
Method for the hierarchical comparison of schematics and layouts of electronic components
Method of layout processing including layout data verification
Method to efficiently reduce the number of connections in a circuit Patent #: 5257201
ApplicationNo. 085639 filed on 06/30/1993
US Classes:716/5Design verification (e.g., wiring line capacitance, fan-out checking, minimum path width)
ExaminersPrimary: Trans, Vincent N.
Attorney, Agent or Firm
International ClassG06F 017/50
AbstractA method for determining whether multiple representations of a design of a circuit are consistent with each other, where the circuit includes multiple devices with channels for conducting electrical current. Each representations includes a list of device elements that describe the devices and node elements that describe the nodes which interconnect the devices. The method includes modifying each of the lists by: (1) analyzing the device elements and the node elements to identify at least one channel connected region of said circuit (where a channel connected region includes the subset of the devices that have channels interconnected by a subset of the nodes), (2) defining, for each channel connected region, a channel connected region element that describes the subset of the devices and the subset of the nodes in the region, and (3) replacing the device elements of each subset of devices and the node elements of each subset of nodes in the lists with the channel connected region elements. Thereafter, the modified lists are compared as a basis for determining whether the representations are consistent with each other.