U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

System for increasing the efficiency of communications between controller and plurality of host computers by prohibiting retransmission of the same message for predetermined period of time

Patent 5461720 Issued on October 24, 1995. Estimated Expiration Date: Icon_subject October 24, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Fast write operations
Patent #: 4916605
Issued on: 04/10/1990
Inventor: Beardsley, et al.

Device initiated partial system quiescing
Patent #: 4970640
Issued on: 11/13/1990
Inventor: Beardsley, et al.

Apparatus for suppressing an error report from an address for which an error has already been reported
Patent #: 5226150
Issued on: 07/06/1993
Inventor: Callander, et al.

Data processing system with tree and list data structure
Patent #: 5230048
Issued on: 07/20/1993
Inventor: Moy

Interruption controlling system using timer circuits
Patent #: 5280628
Issued on: 01/18/1994
Inventor: Nakayama

Method and system for utilizing benign fault occurrence to measure interrupt-blocking times
Patent #: 5301312
Issued on: 04/05/1994
Inventor: Christopher, Jr., et al.

Multiprocessor system and interruption control device for controlling interruption requests between processors and peripheral devices in the multiprocessor system
Patent #: 5317747
Issued on: 05/31/1994
Inventor: Mochida, et al.

Information processor with delayed interrupt device Patent #: 5363506
Issued on: 11/08/1994
Inventor: Fukuoka

Inventors

Application

No. 949671 filed on 09/23/1992

US Classes:

711/112, Direct access storage device (DASD)710/74, For data storage device711/147, Shared memory area714/16, Forward recovery (e.g., redoing committed action)714/43Bus, I/O channel, or network path component fault

Examiners

Primary: Lee, Thomas C.
Assistant: Meky, Moustafa M.

Attorney, Agent or Firm

International Class

G06F 015/02

Abstract

A method and system for enhancing the efficiency of communication between multiple host computers and a storage system controller via multiple communication channels. After detecting a transmission of a specific message from the storage system controller to a selected host computer, channel data bits corresponding to that particular communication channel are set within preliminary control words which are stored in temporary storage locations. A timer circuit is coupled to the temporary storage locations and periodically resets the channel data bits. A final control word is then calculated by combining the channel data bits from all of the preliminary control words. A control circuit is then utilized to prohibit the retransmission of the specific message from the storage system controller to the selected host computer for a predetermined minimum period of time in response to the state of the channel data bits within the final control word. Communication efficiency is increased by eliminating unnecessary transmissions of a specific message.

Other References

  • Mischa Schwartz, "Telecommunication Networks", 1987, pp. 372-37
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