Process for high density flash EPROM cell
April 25, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod for making an electrically erasable programmable read only memory cell having a three dimensional floating gate Method of making a pleated floating gate trench EPROM Method of making a three-dimensional memory cell with integral select transistor Vertical memory cell array and method of fabrication Method of fabricating a high density EPROM cell on a trench wall Vertical floating-gate transistor Self-aligned stacked gate EPROM cell using tantalum oxide control gate dielectric Patent #: 5304503 InventorApplicationNo. 231811 filed on 04/25/1994US Classes:438/259, Including forming gate electrode in trench or recess in substrate257/315, With floating gate electrode257/E21.422, With floating gate (EPO)257/E21.693, For vertical channel (EPO)438/261Multiple interelectrode dielectrics or nonsilicon compound gate insulatorExaminersPrimary: Chaudhuri, OlikAssistant: Booth, Richard A. Attorney, Agent or FirmInternational ClassesH01L 021/265H01L 021/824.7 AbstractA method and structure for manufacturing a high-density EPROM or flash memory cell is described. A structure having silicon islands is formed from a device-well that has been implanted with a first conductivity-imparting dopant, over a silicon substrate. A first dielectric layer surrounds the vertical surfaces of the silicon islands, whereby the first dielectric layer is a gate oxide. A first conductive layer is formed over vertical surfaces of the first dielectric layer, and acts as the floating surrounding-gate for the memory cell. A source region is formed in the device-well by implanting with a second and opposite conductivity-imparting dopant to the first conductivity-imparting dopant, and surrounds the base of the silicon islands. A drain region is in the top of the silicon islands, formed by implanting with a second and opposite conductivity-imparting dopant to the first conductivity-imparting dopant. A thin dielectric layer surrounds the silicon islands, over the source region and under the first conductive layer, and acts as a tunnel oxide for the memory cell. A second dielectric layer is formed over vertical surfaces of the first conductive layer, and horizontally over the source region, and is an interpoly dielectric. A second conductive layer is formed over vertical surfaces of the second dielectric layer, and is the control gate for the memory cell.Other References
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