Architecture and interconnect scheme for programmable logic circuits
August 3, 2013. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesProgrammable arrays Programmable, asynchronous logic cell and array Programmable logic device Configurable electrical circuit having configurable logic elements and configurable interconnects Programmable logic cell and array Semi-conductor integrated circuits/systems Programmable logic device having a plurality of programmable logic arrays arranged in a mosaic layout together with a plurality of interminglingly arranged interfacing blocks Programmable logic cell and array Configurable cellular array Programmable logic element interconnections for programmable logic array integrated circuits Patent #: 5260610 InventorAssigneeApplicationNo. 101197 filed on 08/03/1993US Classes:326/41, Significant integrated structure, layout, or layout interconnections326/39, Array (e.g., PLA, PAL, PLD, etc.)716/14, Detailed routing (e.g., channel routing, switch box routing)716/16, PLA, PLD, FPGA, OR MCM716/17Programmable integrated circuit (e.g., basic cell, standard cell, macrocell)ExaminersPrimary: Hudspeth, DavidAssistant: Santamauro, Jon Attorney, Agent or FirmForeign Patent References
International ClassH03K 019/177AbstractAn architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells which perform logical functions on input signals. Programmable intraconnections provide connectability between each output of a cell belonging to a logical cluster to at least one input of each of the other cells belonging to that logical cluster. A set of programmable block connectors are used to provide connectability between logical clusters of cells and accessibility to the hierarchical routing network. An uniformly distributed first layer of routing network lines is used to provide connections amongst sets of block connectors. An uniformly distributed second layer of routing network lines is implemented to provide connectability between different first layers of routing network lines. Switching networks are used to provide connectability between the block connectors and routing network lines corresponding to the first layer. Other switching networks provide connectability between the routing network lines corresponding to the first layer to routing network lines corresponding to the second layer. Additional uniformly distributed layers of routing network lines are implemented to provide connectability between different prior layers of routing network lines.Other References
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