Thermally enhanced semiconductor device having exposed backside and method for making the same
January 10, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSolder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and process for making Semiconductor resin package structure Semiconductor device Flexible carrier for an electronic device Structure and method of packaging a semiconductor device Molded ring integrated circuit package Three-dimensional multi-chip pad array carrier Overmolded semiconductor device having solder ball and edge lead connective structure Chip carrier with protective coating for circuitized surface Area array semiconductor device having a lid with functional contacts InventorsAssigneeApplicationNo. 179892 filed on 01/10/1994US Classes:361/704, Thermal conduction174/16.3, With heat sink257/700, Multiple contact layers separated from each other by insulator means and forming part of a package or housing (e.g., plural ceramic layer package)257/706, With heat sink257/778, Flip chip257/787, ENCAPSULATED257/E21.503, Encapsulation of active face of flip chip device, e.g., under filling or under encapsulation of flip-chip, encapsulation perform on chip or mounting substrate (EPO)257/E21.504, Moulds (EPO)257/E23.069, Spherical bumps on substrate for external connection, e.g., ball grid arrays (BGA) (EPO)257/E23.125, Substrate forming part of encapsulation (EPO)361/714, Through component housing361/717, For active solid state devices361/722For electronic circuitExaminersPrimary: Thompson, Gregory D.Attorney, Agent or FirmForeign Patent References
International ClassH05K 007/20AbstractA thermally enhanced semiconductor device (10) having an exposed backside (22) is described. In one embodiment, a PC board substrate (12) is provided having a pattern of conductive traces (14) on both upper and lower surfaces of the substrate. Electrical continuity is maintained between the two surfaces with conductive vias (16). A semiconductor die (18) is flip-mounted to the upper surface of the substrate. Solder bumps (26) electrically connect the die to the conductive traces, and an underfill (28) couples the active side (20) of the die to the upper surface of the substrate. A package body (40) is formed around the perimeter (24) of the die leaving the inactive backside exposed for enhanced thermal dissipation. The inactive backside can also be coupled to a heat sink for increased thermal dissipation. A plurality of solder balls (42) electrically connected to the conductive traces is attached to the lower surface of the substrate. | |
