Abstract

A system with an apparatus that can be used in the compounding of instructions for CISC architectures and architectures with other attributes, including RISC. The compounding is performed before instruction execution and it results in a compound instruction program that can be executed in a parallel fashion on appropriate instruction execution hardware. In particular, the proposed apparatus provides compounding capability for architectures that allow the intermingling of instructions and data, contain variable length instructions, and allow modifications of the instruction stream. The system provides for differing and partial reference point information. An embodiment of the proposed apparatus handles the worst-case situation when it is not known which text bytes are instructions and which are data. If some information is known, the system can be simplified. The apparatus as presented provides compounds capability for any number of instructions. The system is developed particularly for machines with a S/370 instruction set, for which a number of examples are given. A backward compounding apparatus is provided. Multiple compound units and logical ORing of sequences provides system support for more difficult organizations.

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