Method and apparatus for testing circuit boards
Method and apparatus for generating control signals
Registered RAM array with parallel and serial interface
Semiconductor apparatus including semiconductor integrated circuit and operating method thereof
Semiconductor integrated circuit device comprising scan paths having individual controllable bypasses
Method and apparatus for data transfer to and from devices through a boundary-scan test access port
Test driver for connecting a standard test port integrated circuit chip to a controlling computer
Single chip IC tester architecture
Boundary-scan test method and apparatus for diagnosing faults in a device under test
ApplicationNo. 968104 filed on 10/29/1992
US Classes:714/727, Boundary scan714/736Device response compared to expected fault-free response
ExaminersPrimary: Voeltz, Emanuel T.
Assistant: Choi, Kyle J.
Attorney, Agent or Firm
International ClassH04B 017/00
AbstractA method and apparatus provides improved modes of operation of a standard test bus based on a standard boundary scan architecture which minimizes the number of bits required to be serially scanned into the controllers of the various devices connected to the bus by temporarily disabling scan paths not required to be utilized. Means for continuously verifying the inoperative state of test logic and for diagnosing test logic faults are also described.