Digital phase-lock loop having an estimator and predictor of error
Apparatus for low skew system clock distribution and generation of 2X frequency clocks
Digital phase-locked loop using a tapped delay line in a phase meter
Digital phase lock loop for a gate array
High resolution, multi-frequency digital phase-locked loop
Skew-free clock signal distribution network in a microprocessor Patent #: 5307381
ApplicationNo. 890937 filed on 05/29/1992
US Classes:713/503, Correction for skew, phase, or rate331/17Particular error voltage control (e.g., intergrating network)
ExaminersPrimary: Lee, Thomas C.
Assistant: Dinh, D.
Attorney, Agent or Firm
International ClassesG06F 001/00
AbstractA circuit for use in high performance microprocessor systems which eliminates skew between a clock signal internal to the microprocessor core and inputs generated by a clock signal external to the microprocessor core. The circuit includes a phase locked loop (PLL), a delay line and a clock driver. The PLL locks and deskews the external clock edge to that of the internal clock to thereby provide an overall reduction of the setup and hold time window to satisfy the tight I/O timings required by high performance microprocessor systems. By incorporating the same PLL in all the closely coupled components of the microprocessor core, similar temperature and power supply tracking of such components is achieved. The PLL is a charge-pump based circuit of the type known in the art incorporating a phase detector, charge pump, loop filter and voltage controlled oscillator (VCO). However, the inclusion of the delay line in the feedback path of the PLL provides advantages not available from PLLs without such a delay line. A programmable tap is provided in the delay line which allows the I/O circuitry of the microprocessor to work with either CMOS or TTL input specifications. Specifically, compensation is provided for the differences in propagation delay between CMOS and TTL input buffers.