U.S. patents available from 1976 to present.
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Apparatus for recovering data and clock information from an encoded serial data stream

Patent 5446765 Issued on August 29, 1995. Estimated Expiration Date: Icon_subject August 17, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Single channel serial data receiver
Patent #: 5172397
Issued on: 12/15/1992
Inventor: Llewellyn

Frequency independent encoding technique and apparatus for digital communications Patent #: 5303265
Issued on: 04/12/1994
Inventor: McLean

Inventor

Assignee

Application

No. 292629 filed on 08/17/1994

US Classes:

375/359, Self-synchronizing signal (self-clocking codes, etc.)341/70, To or from bi-phase level code (e.g., split phase code, Manchester code)341/71, To or from bi-phase space or mark codes (e.g., double frequency code, FM code)375/282, Biphase (manchester codes)714/755Double encoding codes (e.g., product, concatenated)

Examiners

Primary: Chin, Stephen
Assistant: Le, Amanda T.

Attorney, Agent or Firm

International Class

H04L 007/02

Abstract

The invention doubles the bit rate for a given media bandwidth as compared to, for example, Manchester encoding. It is applicable to serial transmission or storage of digital data. An arbitrary NRZ data stream is first encoded by a pre-encoding method, such as Manchester, that combines clock and data to represent a single NRZ bit in one clock cycle. A toggle flip flop then re-encodes the pre-encoded waveform, thus generating a double toggle (DT) encoded waveform, which spreads the spectral energy over a larger bandwidth and encodes two NRZ data bits within one transmission clock cycle. In the case of Manchester pre-encoding, data is decoded by determining if there are transitions nearly synchronous with an edge of the recovered clock. For other pre-encoding methods, decoded data is determined by the length of the transition period and the edge polarity of the recovered clock at the leading edge of the transition within the DT encoded waveform. DC offset is reduced by substitution within and inversion of the DT encoded waveform. DC offset compensation of the encoded waveform is either removed prior to data decoding or after a data pre-decoding step; in either case the apparatus searches and detects predetermined substituted patterns in order to correct for the inversion or substitution. Further, a clock state generator is disclosed that uses precision silicon delays in order to generate clock states and quickly synchronize the states to the received encoded waveform. The clock states generate the recovered clocks required to decode data from the encoded waveform.

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