U.S. patents available from 1976 to present.
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Optimizing compiler for computers

Patent 5442790 Issued on August 15, 1995. Estimated Expiration Date: Icon_subject March 9, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Multinode reconfigurable pipeline computer
Patent #: 4811214
Issued on: 03/07/1989
Inventor: Nosenchuck ,   et al.

Parallelization compile method and system Patent #: 5151991
Issued on: 09/29/1992
Inventor: Iwasawa, et al.

Inventor

Assignee

Application

No. 208488 filed on 03/09/1994

US Classes:

717/155, Data flow analysis717/146, Including intermediate code717/159Code restructuring

Examiners

Primary: Kriess, Kevin A.
Assistant: Chaki, Kakali

Attorney, Agent or Firm

International Class

G06F 009/45

Abstract

A method is described for compiling a source code listing into an object code listing and comprises the steps of: extracting a block of source code statements from a source code listings; mapping each source code statement in the block into a wide intermediate code (WIC) statement in object form, a WIC statement defining a series of machine actions to perform the function(s) called for by the source code statement; performing an initial approximate simulation of each WIC statement in a block and deriving performance results from the simulation of each WIC statement and the block of WIC statements; dependent upon the performance results, revising the WIC statements in the block in accordance with one of a group of code transform algorithms and heuristics in an attempt to improve the code's performance results; and repeating the approximate simulation to determine if the performance results have been improved and, if so, proceeding to another of the algorithms to enable further revision of the WIC statements, until a decision point is reached, and at such time, producing the revised WIC statements in object code form.

Other References

  • The Effect of Restructuring Compilers on Program Performance for High-Speed Computers, Cytrol et al., Comp. Physics Comm., 1985, pp. 39-48
  • Experiments in Optimizing FP: Ryder et al., IEEE Trans. on Software Engg., vol. 14, No. 4, Apr. 1988, pp. 444-454
  • P. B. Schneck et al., "An Optimizing Compiler", Sep. 1972, The Computer Journal, pp. 322-330
  • David J. Kuck et al., "Measurements of Parallelism in Ordinary Fortran Programs" Jan. 1974, The Computer Journal pp. 37-46
  • Joseph A. Fisher, Student Member, IEEE, "Trace Scheduling: A Technique for Global Microcode Compaction" IEEE Transactions on Computers, vol. 30 Jul. 1981 pp. 478-490. No. 7
  • Joseph A. Fisher, Yale University, "The VLIW Machine: A Multiprocessor for Compiling Scientific Code" 1984 IEEE pp. 45-53, Jul
  • Rajiv Gupta et al. "Compliation Techniques for a Reconfigurable LIW Architecture" The Journal of Supercomputing 3, pp. 271-304 1989
  • Pei-Zong Lee et al. "Mapping Nested Loop Algorithms into Multidimensional Systolic Arrays" IEEE Transactions on Parallel and Distributed Systems Jan. 1990 pp. 64-76 vol. 1. No.
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