Patent ReferencesMultinode reconfigurable pipeline computer Parallelization compile method and system Patent #: 5151991 InventorAssigneeApplicationNo. 208488 filed on 03/09/1994US Classes:717/155, Data flow analysis717/146, Including intermediate code717/159Code restructuringExaminersPrimary: Kriess, Kevin A.Assistant: Chaki, Kakali Attorney, Agent or FirmInternational ClassG06F 009/45AbstractA method is described for compiling a source code listing into an object code listing and comprises the steps of: extracting a block of source code statements from a source code listings; mapping each source code statement in the block into a wide intermediate code (WIC) statement in object form, a WIC statement defining a series of machine actions to perform the function(s) called for by the source code statement; performing an initial approximate simulation of each WIC statement in a block and deriving performance results from the simulation of each WIC statement and the block of WIC statements; dependent upon the performance results, revising the WIC statements in the block in accordance with one of a group of code transform algorithms and heuristics in an attempt to improve the code's performance results; and repeating the approximate simulation to determine if the performance results have been improved and, if so, proceeding to another of the algorithms to enable further revision of the WIC statements, until a decision point is reached, and at such time, producing the revised WIC statements in object code form.Other References
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