Decoded instruction cache architecture with each instruction field in multiple-instruction cache line directly connected to specific functional unit
December 22, 2013. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMicroprogrammed, multipurpose processor having controllable execution speed Cache memory architecture with decoding Mechanism for creating dependency free code for multiple processing elements Small instruction cache using branch target table to effect instruction prefetch Cache memory consistency control with explicit software instructions Method and apparatus for facilitating instruction processing of a digital computer Prefetching system for a cache having a second directory for sequentially accessed blocks Instruction issuing mechanism for processors with multiple functional units Bus master having selective burst deferral Hierarchical priority branch handling for parallel execution in a parallel processor InventorsAssigneeApplicationNo. 173136 filed on 12/22/1993US Classes:712/215, Simultaneous issuance of multiple instructions712/24, Long instruction word712/213Predecoding of instruction componentExaminersPrimary: Treat, William M.Attorney, Agent or FirmForeign Patent References
International ClassG06F 009/30AbstractA general purpose computer system is equipped with apparatus for enabling a processor to provide efficient execution of multiple instructions per clock cycle. The major feature is a decoded instruction cache with multiple instructions per cache line. During run time cache hits, the decode logic fills the cache line with instructions up to its limit. During run time cache misses, the cache line enables the processor to dispatch multiple instructions during one clock cycle. Hereby is achieved high performance with a simple, but still powerful, decode and dispatch logic.An important feature of the instruction cache is that it holds the target addresses for the next instructions. No separate address logic is needed to proceed in the program execution during cache hits. A conditional branch holds its alternative target address in a separate field. This enables the processor, to a large degree, to be independent of the conditional branch bottleneck.Other References
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