Method for connecting electronic components with dummy patterns
Semiconductor integrated circuit device in which a semiconductor chip is mounted with solder bumps for mounting to a wiring substrate
Semiconductor integrated circuit with dummy patterns
Planarization process utilizing three resist layers
Semiconductor integrated circuit device having a gate array with a RAM and by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array
Manufacturing method for a semiconductor device having a bias sputtered insulating film Patent #: 5182235
ApplicationNo. 214852 filed on 03/18/1994
US Classes:438/631, Having planarization step257/211, Multi-level metallization257/E21.244, Involving dielectric removal step (EPO)257/E21.58, Planarizing dielectric (EPO)438/926DUMMY METALLIZATION
ExaminersPrimary: Quach, T. N.
Attorney, Agent or Firm
Foreign Patent References
International ClassH01L 021/283
AbstractA method for fabricating a metallurgy system is described wherein a first level of metallurgy is formed, having a plurality of close uniformly spaced conductive line of a predetermined width, and wherein there are included larger gaps between the conductive lines. The areas in the larger gaps are filled with dummy lines, where the gap is equal to or greater than three times the feature size or alternatively the width of the conductive lines.
Field of SearchMulti-level metallization