U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Semiconductor integrated circuit apparatus including supply voltage conversion circuit

Patent 5436586 Issued on July 25, 1995. Estimated Expiration Date: Icon_subject November 15, 2013. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Power on reset pulse generating circuit sensitive to rise time of the power supply
Patent #: 4818904
Issued on: 04/04/1989
Inventor: Kobayashi

Method of and apparatus for reducing current of semiconductor memory device
Patent #: 4933902
Issued on: 06/12/1990
Inventor: Yamada, et al.

Semiconductor integrated circuit device
Patent #: 4994689
Issued on: 02/19/1991
Inventor: Kikuda, et al.

NMOS transistor having inversion layer source/drain contacts
Patent #: 4994869
Issued on: 02/19/1991
Inventor: Matloubian, et al.

Semiconductor memory with power-on reset controlled latched row line repeaters
Patent #: 5121358
Issued on: 06/09/1992
Inventor: Slemmer, et al.

Circuit having charge compensation and an operation method of the same
Patent #: 5151614
Issued on: 09/29/1992
Inventor: Yamazaki, et al.

Power-on-reset circuit including integration capacitor
Patent #: 5166545
Issued on: 11/24/1992
Inventor: Harrington

Power on reset circuit for semiconductor integrated circuit device
Patent #: 5177375
Issued on: 01/05/1993
Inventor: Ogawa, et al.

Dynamic random access memory device capable of performing test mode operation and method of operating such memory device
Patent #: 5270977
Issued on: 12/14/1993
Inventor: Iwamoto, et al.

Circuit for decreasing current consumption in data output circuit in case one of two supply voltages fails
Patent #: 5291454
Issued on: 03/01/1994
Inventor: Yamasaki, et al.

More ...

Inventor

Application

No. 151721 filed on 11/15/1993

US Classes:

327/530, With specific source of supply or bias voltage327/198, Initializing, resetting, or protecting a steady state condition327/535, Having stabilized bias or power supply level365/189.09, Including reference or bias voltage generator365/226POWERING

Examiners

Primary: Callahan, Timothy P.
Assistant: Phan, Trong

Attorney, Agent or Firm

Foreign Patent References

  • 3936675A1 DE. 06/20/1990

International Classes

G05F 001/10
H03K 003/02
G11C 007/00

Foreign Application Priority Data

1990-07-31 JP

Abstract

Disclosed is a DRAM including a power-on reset signal generating circuit for outputting a voltage of a predetermined level for a definite period by utilizing a rise of an external supply voltage, and a supply voltage conversion circuit for lowering the external supply voltage to a constant voltage. In this DRAM, the power-on reset signal generating circuit is driven by the external supply voltage not an output voltage of the supply voltage conversion circuit. The output voltage of the supply voltage conversion circuit is applied to various internal circuits including smaller-scale MOS transistors, to drive these internal circuits. Since the supply voltage conversion circuit often includes circuit components with a large time constant in order to decrease power consumption, the output voltage of the supply voltage conversion circuit rises rather slowly than the external supply voltage. However, the power-on reset signal generating circuit receives the external supply voltage as a driving voltage and hence immediately outputs a normal one-shot pulse in response to the supply of power to the DRAM.

Other References

  • IEEE Journal of Solid-State Circuits, "A 45-ns 16 Mbit DRAM with Triple-Well Structure", vol. 24, No. 5, Oct. 1989, pp. 1170-1175
  • IEEE Journal of Solid-State Circuits, "A New On-Chip Voltage Converter for Submicrometer High-Density DRAM's," vol. sc-22, No. 3, Jun. 1987, pp. 437-441
  • IEEE Journal of Solid-State Circuits, "Circuit Techniques for a VLSI Memory", vol. sc-18, No. 5, Oct. 1983, pp. 463-470
  • IEEE Journal of Solid-State Circuits, "Dual-Operating-Voltage Scheme for a Single 5-V 16-Mbit DRAM", vol. 23, No. 5, Oct. 1988, pp. 1128-1132
  • IEEE Journal of Solid-State Circuits "A Tunable CMOS-DRAM Voltage Limiter with Stabilized Feedback Amplifier", vol. 25, No. 5, Oct. 1990, pp. 1129-1135
  • IEEE Journal of Solid-State Circuits, "A 4-Mbit DRAM with Half-Internal-Voltage Bit-Line Precharge", vol. sc-21, No. 5, Oct. 1986, pp. 612-61
PatentsPlus Images
Enhanced PDF formats
loading...
PatentsPlus: add to cart
PatentsPlus: add to cartSearch-enhanced full patent PDF image
$9.95more info
PatentsPlus: add to cart
PatentsPlus: add to cartIntelligent turbocharged patent PDFs with marked up images
$18.95more info
 
Sign InRegister
Username  
Password   
forgot password?