Method of forming an integrated circuit assembly
Substrate for interconnecting electronic integrated circuit components having a repair arrangement enabling modification of connections to a mounted chip device
Sealing and stress relief layers and use thereof
Structure and method for corrosion and stress-resistant interconnecting metallurgy
Ceramic substrate having a protective coating thereon and a method for protecting a ceramic substrate
Multilayer structure and its fabrication method
Method for fabricating printed circuits
Semiconductor device having an opening and method of manufacturing the same Patent #: 5291374
ApplicationNo. 102027 filed on 08/03/1993
US Classes:174/265, Preform in hole174/257, Conducting (e.g., ink)174/261, With particular conductive connection (e.g., crossover)174/262, Feedthrough257/E23.069, Spherical bumps on substrate for external connection, e.g., ball grid arrays (BGA) (EPO)257/E23.072, Characterized by materials (EPO)257/E23.173Multilayer substrates (EPO)
ExaminersPrimary: Picard, Leo P.
Assistant: Thomas, L.
Attorney, Agent or Firm
Foreign Patent References
International ClassH06K 001/02
AbstractAn electrical interconnect structure for connecting a substrate to the next level of packaging or to a semiconductor device. The interconnect structure includes at least two layers of polymeric material, one of the layers having a capture pad and the second of the layers having a bonding pad electrically connected to the capture pad. The bonding pad and the second layer of polymeric material are at the same height so that the bonding pad is level with the second layer of polymeric material. Finally, there is a cap of electrically conducting metallization on the bonding pad and extending beyond the second layer of polymeric material. The cap is of a different composition than the bonding pad.