U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Interconnect structure having improved metallization

Patent 5436412 Issued on July 25, 1995. Estimated Expiration Date: Icon_subject August 3, 2013. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Method of forming an integrated circuit assembly
Patent #: 3959874
Issued on: 06/01/1976
Inventor: Coucoulas

Substrate for interconnecting electronic integrated circuit components having a repair arrangement enabling modification of connections to a mounted chip device
Patent #: 4371744
Issued on: 02/01/1983
Inventor: Badet ,   et al.

4751349

Sealing and stress relief layers and use thereof
Patent #: 4880684
Issued on: 11/14/1989
Inventor: Boss, et al.

Structure and method for corrosion and stress-resistant interconnecting metallurgy
Patent #: 5175609
Issued on: 12/29/1992
Inventor: DiGiacomo, et al.

Ceramic substrate having a protective coating thereon and a method for protecting a ceramic substrate
Patent #: 5196251
Issued on: 03/23/1993
Inventor: Bakhru, et al.

Multilayer structure and its fabrication method
Patent #: 5219639
Issued on: 06/15/1993
Inventor: Sugawara, et al.

Method for fabricating printed circuits
Patent #: 5235139
Issued on: 08/10/1993
Inventor: Bengston, et al.

Semiconductor device having an opening and method of manufacturing the same Patent #: 5291374
Issued on: 03/01/1994
Inventor: Hirata, et al.

Inventors

Application

No. 102027 filed on 08/03/1993

US Classes:

174/265, Preform in hole174/257, Conducting (e.g., ink)174/261, With particular conductive connection (e.g., crossover)174/262, Feedthrough257/E23.069, Spherical bumps on substrate for external connection, e.g., ball grid arrays (BGA) (EPO)257/E23.072, Characterized by materials (EPO)257/E23.173Multilayer substrates (EPO)

Examiners

Primary: Picard, Leo P.
Assistant: Thomas, L.

Attorney, Agent or Firm

Foreign Patent References

  • 0380289A3 EP 01/21/1990
  • 0504411A1 EP 09/21/1991
  • 0536418A1 EP 04/21/1992
  • 60138948 JP 12/21/1983
  • WO92/20100 WO 07/21/1991

International Class

H06K 001/02

Abstract

An electrical interconnect structure for connecting a substrate to the next level of packaging or to a semiconductor device. The interconnect structure includes at least two layers of polymeric material, one of the layers having a capture pad and the second of the layers having a bonding pad electrically connected to the capture pad. The bonding pad and the second layer of polymeric material are at the same height so that the bonding pad is level with the second layer of polymeric material. Finally, there is a cap of electrically conducting metallization on the bonding pad and extending beyond the second layer of polymeric material. The cap is of a different composition than the bonding pad.

Other References

  • IBM Research Disclosure, "Combination Process for Final Metal Lines and Metal Terminals", Disclosed anonymously; Oct. 1992, No. 342, p. 753
  • IEEE, "Production of MCP Chip Carriers", M. E. Williams, 0569-5503/90-0000-0408 May, 199
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