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US Patent 5434093 - Inverted spacer transistor
US Patent Issued on July 18, 1995
Estimated Patent Expiration Date:
August 10, 2014Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
Estimated Patent Expiration Date:
August 10, 2014Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.AbstractA method for forming narrow length transistors by forming a trench in a first layer over a semiconductor substrate. Spacers are then formed within the trench and a gate dielectric is formed between the spacers at the bottom of the trench on the semiconductor substrate. The trench is then filled with a gate electrode material which is chemically-mechanically polished back to isolate the gate electrode material within the trench, and the first layer is removed leaving the gate dielectric, gate electrode and spacers behind.Other References
| Inventors
ApplicationNo. 288332 filed on 08/10/1994US Classes:438/300, Having elevated source or drain (e.g., epitaxially formed source or drain, etc.)257/E21.43, Recessing gate by adding semiconductor material at source (S) or drain (D) location, e.g., transist or with elevated single crystal S and D (EPO)257/E21.434, With initial gate mask or masking layer complementary to prospective gate location, e.g., with dummy source and drain contacts (EPO)257/E29.04, Of field-effect transistors with insulated gate (EPO)257/E29.051, With insulated gate (EPO)257/E29.135, Characterized by length or sectional shape (EPO)438/302, Oblique implantation438/303, Utilizing gate sidewall structure438/305Plural doping stepsExaminersPrimary: Hearn, Brian E.Assistant: Dang, Trung Attorney, Agent or FirmUS Patent References4378627, Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodesIssued on: 04/05/1983 Inventor: Jambotkar4895520, Method of fabricating a submicron silicon gate MOSFETg21 which has a self-aligned threshold implant Issued on: 01/23/1990 Inventor: Berg5034351, Process for forming a feature on a substrate without recessing the surface of the substrate Issued on: 07/23/1991 Inventor: Sun, et al.5047361, NMOS transistor having inversion layer source/drain contacts Issued on: 09/10/1991 Inventor: Matloubian, et al.5082794, Method of fabricating MOS transistors using selective polysilicon deposition Issued on: 01/21/1992 Inventor: Pfiester, et al.5091763, Self-aligned overlap MOSFET and method of fabrication Issued on: 02/25/1992 Inventor: Sanchez5175119, Method of producing insulated-gate field effect transistor Issued on: 12/29/1992 Inventor: Matsutani5217910, Method of fabricating semiconductor device having sidewall spacers and oblique implantation Issued on: 06/08/1993 Inventor: Shimizu, et al.5223445Large angle ion implantation method Issued on: 06/29/1993 Inventor: Fuse International ClassH01L 021/265 |
