Input/output (I/O) bidirectional buffer for interfacing I/O ports of a field programmable interconnection device with array ports of a cross-point switch
October 13, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesInput/output interface connector circuit for repowering and isolation Bus connection system Universal arrangement for the exchange of data between the memories and the processing devices of a computer Intersystem cycle control logic Bus request buffer circuit for interfacing between field maintenance processor and device specific adaptor Power sequencer Fault-tolerant multiprocessor arrangement Method of using electronically reconfigurable logic circuits Bi-directional bus repeater I/O buffering system to a programmable switching apparatus Patent #: 5282271 InventorsAssigneeApplicationNo. 960965 filed on 10/13/1992US Classes:326/82, Current driving (e.g., fan in/out, off chip driving, etc.)710/317CrossbarExaminersPrimary: Lee, Thomas C.Assistant: Barry, Lance Leonard Attorney, Agent or FirmInternational ClassesG06F 013/00H03K 017/16 AbstractA bi-directional buffer includes first and second unidirectional buffers connected for retransmitting signals in opposite directions between first and second buses. When an external bus driver pulls the first bus low, the first unidirectional buffer pulls the second bus low and generates a signal inhibiting the second unidirectional buffer from actively driving the first bus. When the external bus driver allows the first bus to return to the high logic level, the first unidirectional buffer temporarily supplies a high charging current to the second bus to quickly pull it up. Similarly, when an external bus driver pulls the second bus low, the second unidirectional buffer pulls the first bus low and generates a signal inhibiting the first unidirectional buffer from actively driving the second bus. When the external bus driver allows the second bus to return to the high logic level, the second buffer temporarily supplies a high charging current to the first bus to quickly pull it up. The bi-directional buffer includes a register for storing and reading out data representing successive logic states of a signal on the first bus, thereby providing a history of data appearing on the bus.Field of SearchCurrent driving (e.g., fan in/out, off chip driving, etc.) | |
