Field programmable gate array with built-in bitstream data expansion
Patent 5426379 Issued on June 20, 1995. Estimated Expiration Date: 
July 29, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
July 29, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References Re34363 3473160 In-system programmable logic device with four dedicated terminals Configuration control circuit for programmable logic devices Patent #: 4940909 InventorApplicationNo. 283122 filed on 07/29/1994US Classes:326/39, Array (e.g., PLA, PAL, PLD, etc.)326/38Having details of setting or programming of interconnections or logic functionsExaminersPrimary: Westin, Edward P.Assistant: Calogero, Stephen Attorney, Agent or FirmInternational ClassesG06F 007/38H03K 019/173 AbstractA programmable gate array comprises an array of configurable logic blocks. Each configurable logic block is controlled by one or more rows and columns of memory cells in a memory array. According to the invention, an older bitstream may be used without modification in a newer programmable gate array. A frame register includes a plurality of active memory locations called frame bits which correspond to columns of memory cells within the memory array and at least one spare frame bit which does not correspond to a column of memory cells within the memory array. A similar configuration of row pointer cells comprises a shift register for enabling row by row addressing of the memory array. Spare frame bits and spare pointer cells are selectively either loaded or bypassed by programmable selector circuits, permitting expansion of the memory array in future programmable gate arrays, and thereby allowing additional functionality to be added to later versions of the programmable gate array without requiring designers of gate array applications to modify bitstreams which they previously designed.Other References
Field of SearchSignificant integrated structure, layout, or layout interconnectionsWith flip-flop or sequential device Array (e.g., PLA, PAL, PLD, etc.) Having details of setting or programming of interconnections or logic functions Including specified plural element logic arrangement Including memory Particular output circuit Sequential output (e.g., tapped delay line) | |
