U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Programmable logic device which stores more than one configuration and means for switching configurations

Patent 5426378 Issued on June 20, 1995. Estimated Expiration Date: Icon_subject April 20, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Integrated circuit programmable cross-point connection technique
Patent #: 4670749
Issued on: 06/02/1987
Inventor: Freeman

Programmable logic array having a changeable logic structure
Patent #: 4876466
Issued on: 10/24/1989
Inventor: Kondou, et al.

In-system programmable logic device
Patent #: 4879688
Issued on: 11/07/1989
Inventor: Turner, et al.

Programmable configurable logic memory
Patent #: 4972105
Issued on: 11/20/1990
Inventor: Burton, et al.

Arrangement for parallel programming of in-system programmable IC logical devices
Patent #: 5329179
Issued on: 07/12/1994
Inventor: Tang, et al.

5336950

Flexible configuration logic array block for programmable logic devices Patent #: 5341044
Issued on: 08/23/1994
Inventor: Ahanin, et al.

Inventor

Application

No. 231009 filed on 04/20/1994

US Classes:

326/39, Array (e.g., PLA, PAL, PLD, etc.)326/38Having details of setting or programming of interconnections or logic functions

Examiners

Primary: Hudspeth, David

Attorney, Agent or Firm

International Class

H03K 019/177

Abstract

A programmable logic device includes a configuration memory expanded to store two or more complete sets of configuration data. A switch on the output of the configuration memory controls the selection of the configuration data applied to the configurable logic block. Each configurable logic block has one data storage device per set of configuration data. The configurable logic blocks may be re-configured within a user's clock cycle.During a first period, the switch on the output of the configuration memory selects and passes configuration data from the first set of configuration data. The configurable routing matrix and configurable logic block are configured according to this first set of configuration data and store results in a first storage device. During a second period, the switch selects and passes the second set of configuration data. Then the configurable routing matrix and configurable logic block are configured according to the second set of configuration data, the function generator performs the second logic function, and the outputs are passed or stored by the second output device. At the end of the last period the function is available to the user.

Other References

  • Xilinx Programmable Gate Array Data Book, 1993, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124
  • Narasimha B. Bhat, Kamal Chaudhary, and Ernest S. Kuh, "Performance-Oriented Fully Routable Dynamic Architecture for a Field Programmable Logic Device", Electronic Research Laboratory, College of Engineering, University of California, Berkeley, 1 Jun. 1993
  • Chi-Yuan Chin, et al., "A Dynamically Reconfigurable Interconnection Chip" Session XX: Special Purpose Accelerators; IEEE International Solid-State Circuits Conference, pp. 276-277, 425; Feb. 27, 1987
  • Andre DeHon, "DPGA-Coupled Microporcessors: Commodity ICs for the Early 21st Century", NE43-791, 545 Technology Square, Cambridge, Mass. 02139, 10 pgs, Jan. 6, 199
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