Method and apparatus for configuration and testing of large fault-tolerant memories Patent #: 5299202
ApplicationNo. 032956 filed on 03/17/1993
US Classes:714/42, Memory or storage device component fault714/719Read-in with read-out and compare
ExaminersPrimary: Canney, Vincent P.
Attorney, Agent or Firm
International ClassG06F 011/00
AbstractDisclosed is a diagnostic procedure for identifying and sizing computer memory, which, in the preferred embodiment of the invention, comprises SIMMs. The procedure comprises the steps of (1) testing a plurality of memory locations in the unit by writing and reading bit patterns to memory locations in succession to determine whether any of the memory locations contains any responding bits and (2) stipulating the unit to be present when a number of the memory locations having any responding bits reaches a predetermined minimum number. The procedure is uniquely designed to detect memory which is not fully functional.