Patent References 3806888 Cache bypass control for operand fetches Operand alignment controls for VFL instructions Command queue apparatus included within a cache unit for facilitating command sequencing Cache memory command buffer circuit Cache/disk subsystem with cache bypass Cache memory architecture with decoding Physical cache unit for computer Cache move-in bypass Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements InventorsApplicationNo. 840464 filed on 02/24/1992US Classes:711/123User data cache and instruction data cacheExaminersPrimary: Harvey, Jack B.Assistant: Lane, Jack A. Attorney, Agent or FirmInternational ClassG06F 013/00AbstractA method of and apparatus for efficiently transferring data between a memory system and an instruction processor having a dedicated cache memory. A read request within the instruction processor for a data element not currently stored within the dedicated cache memory creates a read cache miss condition. A transfer of the eight word block containing the requested data element is initiated from the memory system beginning with the 72 bit double word containing the requested data element. The eight word block of data is placed into a block buffer upon being received by the instruction processor. The instruction processor is permitted to resume instruction execution and access to the cache memory as soon as the requested data element has been received by the block buffer. The eight word data block is transferred from the block buffer to cache memory at the next read cache miss condition. The block buffer has a no save designator for block transfers and other accesses for which near term subsequent access to buffered data is unlikely. Data designated no save is not transferred from the block buffer to the cache memory. | |