Low voltage output buffer with improved speed
July 28, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesIGFET gating circuit having reduced electric field degradation MOS semiconductor integrated circuit in which the production of hot carriers near the drain of a short n channel conductivity type MOS transistor is decreased CMOS output circuit using a low threshold device Output buffer circuit Integrated circuit having a boosted node Output device capable of high speed operation and operating method thereof Patent #: 5343099 InventorAssigneeApplicationNo. 281899 filed on 07/28/1994US Classes:326/58, Complementary FET`s326/81, CMOS327/374, Accelerating switching327/437Complementary metal-oxide semiconductor (CMOS)ExaminersPrimary: Hudspeth, DavidAssistant: Calogero, Stephen Attorney, Agent or FirmInternational ClassesH03K 017/16H03K 019/003 AbstractAn integrated circuit output buffer that operates at a low power supply voltage (e.g., 3.3 volts) shares an I/O bondpad with input circuitry that operates at a higher voltage (e.g., 5 volt) signal level. The higher voltage signal level is typically obtained by connection of the bondpad to a bus that is connected to one or more output buffers on other IC's that operate at the higher power supply voltage level. The inventive output buffer obtains a decreased propagation delay by the use of an additional pull-up transistor in a configuration that protects the low voltage output transistors, including the additional transistor, from the higher voltage signal levels present on the bondpad. In this manner, the output buffer may be used in applications that require the relatively low propagation delay specified for the PCI bus, for example.Other References
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