Logic block with look-up table for configuration and memory
Patent 5414377 Issued on May 9, 1995. Estimated Expiration Date: 
October 18, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
October 18, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesConfigurable logic element Configurable electrical circuit having configurable logic elements and configurable interconnects Output logic macrocell Versatile programmable logic cell for use in configurable logic arrays Patent #: 5245227 InventorApplicationNo. 324858 filed on 10/18/1994US Classes:326/41, Significant integrated structure, layout, or layout interconnections326/40With flip-flop or sequential deviceExaminersPrimary: Westin, Edward P.Assistant: Santamauro, Jon Attorney, Agent or FirmInternational ClassH03K 019/177AbstractA logic block for a field programmable logic device which is of the type using memory bits in a look-up table to provide any function of several inputs, and which uses additional memory bits to control aspects of the configuration, achieves a smaller size by replacing memory bits which control some configuration choices of the logic block with multiplexers which alternately select a default configuration or allow the look-up table memory bits to control the configuration. Thus the memory bits perform an alternate function of serving as a look-up table to generate a function, and controlling gates such as multiplexers, XOR gates or AND gates to generate a function.Other References
Field of SearchTestingMultiplexing Having particular data buffer or latch Having details of setting or programming of interconnections or logic functions Array (e.g., PLA, PAL, PLD, etc.) With flip-flop or sequential device Significant integrated structure, layout, or layout interconnections Significant integrated structure, layout, or layout interconnections | |
